| /external/llvm/lib/CodeGen/ |
| PHIEliminationUtils.cpp | 36 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
37 for (MachineInstr &RI : MRI.reg_instructions(SrcReg)) {
|
| CriticalAntiDepBreaker.h | 36 MachineRegisterInfo &MRI;
|
| DeadMachineInstructionElim.cpp | 34 const MachineRegisterInfo *MRI;
73 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
76 if (!MRI->use_nodbg_empty(Reg))
92 MRI = &MF.getRegInfo();
104 LivePhysRegs = MRI->getReservedRegs();
134 MRI->markUsesInDebugValueAsUndef(Reg);
|
| RegAllocBase.h | 62 MachineRegisterInfo *MRI;
69 : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
|
| ProcessImplicitDefs.cpp | 30 MachineRegisterInfo *MRI;
83 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
143 MRI = &MF.getRegInfo();
144 assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
|
| AggressiveAntiDepBreaker.h | 119 MachineRegisterInfo &MRI;
|
| LLVMTargetMachine.cpp | 169 const MCRegisterInfo &MRI = *getRegisterInfo();
178 MII, MRI, STI);
183 MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context);
185 MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
197 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI,
199 MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
268 const MCRegisterInfo &MRI = *getRegisterInfo();
270 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI,
272 MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
|
| LiveRangeCalc.h | 38 const MachineRegisterInfo *MRI;
128 LiveRangeCalc() : MF(nullptr), MRI(nullptr), Indexes(nullptr),
|
| OptimizePHIs.cpp | 32 MachineRegisterInfo *MRI;
68 MRI = &Fn.getRegInfo();
106 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
113 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
146 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
170 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
173 MRI->replaceRegWith(OldReg, SingleValReg);
|
| UnreachableBlockElim.cpp | 196 MachineRegisterInfo &MRI = F.getRegInfo();
197 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
198 MRI.replaceRegWith(Output, Input);
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineSSAUpdater.h | 55 MachineRegisterInfo *MRI;
|
| FastISel.h | 53 MachineRegisterInfo &MRI;
|
| LiveRegMatrix.h | 41 MachineRegisterInfo *MRI;
|
| LiveVariables.h | 111 MachineRegisterInfo &MRI);
130 MachineRegisterInfo* MRI;
282 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 31 MachineRegisterInfo *MRI;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXFrameLowering.cpp | 44 MachineRegisterInfo &MRI = MF.getRegInfo();
49 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int64RegsRegClass);
58 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int32RegsRegClass);
|
| NVPTXInstrInfo.cpp | 38 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
39 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
40 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
|
| NVPTXReplaceImageHandles.cpp | 316 const MachineRegisterInfo &MRI = MF.getRegInfo();
319 MachineInstr *MI = MRI.getVRegDef(Op.getReg());
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo();
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg))
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRLiveRanges.cpp | 75 MachineRegisterInfo &MRI = MF.getRegInfo();
95 const TargetRegisterClass *RC = MRI.getRegClass(Def.getReg());
|
| SILowerI1Copies.cpp | 72 MachineRegisterInfo &MRI = MF.getRegInfo();
112 MRI.getRegClass(MI.getOperand(0).getReg());
114 MRI.getRegClass(MI.getOperand(1).getReg());
145 MRI.setRegClass(Reg, &AMDGPU::VReg_32RegClass);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo();
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg))
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstPrinter.h | 41 const MCRegisterInfo &MRI;
59 const MCRegisterInfo &mri)
60 : CommentStream(nullptr), MAI(mai), MII(mii), MRI(mri),
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64StorePairSuppress.cpp | 32 const MachineRegisterInfo *MRI;
123 MRI = &MF->getRegInfo();
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 154 MachineRegisterInfo *MRI = &MF.getRegInfo();
155 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
195 MachineRegisterInfo *MRI = &MF.getRegInfo();
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
|
