| /external/llvm/lib/Target/R600/ |
| R600ExpandSpecialInstrs.cpp | 85 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
90 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
93 Mov->getOperand(MovPredSelIdx).setReg(
|
| SIISelLowering.cpp | [all...] |
| /external/vixl/src/a64/ |
| macro-assembler-a64.cc | 144 Mov(rd, 0);
148 Mov(rd, rn);
160 Mov(rd, rn);
163 Mov(rd, immediate);
183 Mov(temp, immediate);
188 Mov(sp, temp);
214 void MacroAssembler::Mov(const Register& rd,
220 Mov(rd, operand.immediate());
235 // Note that mov(w0, w0) is not a no-op because it clears the top word of
243 mov(rd, operand.reg())
[all...] |
| macro-assembler-a64.h | 179 void Mov(const Register& rd, uint64_t imm);
180 void Mov(const Register& rd,
184 Mov(rd, (rd.size() == kXRegSize) ? ~imm : (~imm & kWRegMask));
816 void Mov(const Register& rd, const Register& rn) {
818 mov(rd, rn);
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm32.cc | 126 void Arm32Assembler::mov(Register rd, const ShifterOperand& so, Condition cond) { function in class:art::arm::Arm32Assembler
127 EmitType01(cond, so.type(), MOV, 0, R0, rd, so);
132 EmitType01(cond, so.type(), MOV, 1, R0, rd, so);
623 static_cast<int32_t>(MOV) << kOpcodeShift |
640 static_cast<int32_t>(MOV) << kOpcodeShift |
[all...] |
| assembler_thumb2.cc | 128 void Thumb2Assembler::mov(Register rd, const ShifterOperand& so, Condition cond) { function in class:art::arm::Thumb2Assembler
129 EmitDataProcessing(cond, MOV, 0, R0, rd, so);
134 EmitDataProcessing(cond, MOV, 1, R0, rd, so);
622 bool can_contain_high_register = (opcode == MOV)
657 // The ADD,SUB and MOV instructions that work with high registers don't have
672 // Check for MOV with an ROR.
673 if (opcode == MOV && so.IsRegister() && so.IsShift() && so.GetShift() == ROR) {
684 case MOV:
714 // ADD, SUB, CMP and MOV may be thumb1 only if the immediate is 8 bits.
715 if (!(opcode == ADD || opcode == SUB || opcode == MOV || opcode == CMP))
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 214 Mov(rd, -operand.ImmediateValue());
285 Mov(rd, ~imm);
741 Mov(tmp, float_to_rawbits(imm));
947 void MacroAssembler::Mov(const Register& rd, const Register& rn) {
951 // not X registers. Note that mov(w0, w0) is not a no-op because it clears
954 Assembler::mov(rd, rn);
[all...] |
| macro-assembler-arm64.cc | 82 Mov(rd, 0);
86 Mov(rd, rn);
98 Mov(rd, rn);
101 Mov(rd, immediate);
121 Mov(temp, immediate);
126 Mov(csp, temp);
153 void MacroAssembler::Mov(const Register& rd, uint64_t imm) {
204 // Mov instructions can't move immediate values into the stack pointer, so
234 mov(rd, temp);
241 void MacroAssembler::Mov(const Register& rd
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 750 MachineInstrBuilder Mov;
768 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
771 Mov.addReg(Src);
772 Mov = AddDefaultPred(Mov);
775 Mov = AddDefaultCC(Mov);
778 Mov->addRegisterDefined(DestReg, TRI);
780 Mov->addRegisterKilled(SrcReg, TRI);
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_arm_defs.h | 654 /* MOV dst, src -- reg-reg (or reg-imm8x4) move */
658 } Mov;
716 /* Mov src to dst on the given condition, which may not
803 /* 64-bit FP mov src to dst on the given condition, which may
810 /* 32-bit FP mov src to dst on the given condition, which may
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
