| /external/chromium_org/v8/src/ia32/ |
| disasm-ia32.cc | 338 int SetCC(byte* data);
645 int DisassemblerIA32::SetCC(byte* data) {
1082 data += SetCC(data);
[all...] |
| /external/chromium_org/v8/src/x64/ |
| disasm-x64.cc | 413 int SetCC(byte* data);
804 int DisassemblerX64::SetCC(byte* data) {
[all...] |
| /external/chromium_org/v8/src/x87/ |
| disasm-x87.cc | 338 int SetCC(byte* data);
645 int DisassemblerX87::SetCC(byte* data) {
1082 data += SetCC(data);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 81 setTargetDAGCombine(ISD::SETCC);
175 setOperationAction(ISD::SETCC, MVT::i32, Legal);
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
184 setOperationAction(ISD::SETCC, MVT::f64, Legal);
220 setOperationAction(ISD::SETCC, MVT::i64, Legal);
282 setOperationAction(ISD::SETCC, Ty, Legal);
319 setOperationAction(ISD::SETCC, Ty, Legal);
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 114 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
115 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
222 setTargetDAGCombine(ISD::SETCC);
774 if (Intr->getOpcode() == ISD::SETCC) {
776 SDNode *SetCC = Intr;
777 assert(SetCC->getConstantOperandVal(1) == 1);
778 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
780 Intr = SetCC->getOperand(0).getNode();
[all...] |
| /external/chromium_org/v8/src/arm/ |
| constants-arm.h | 215 SetCC = 1 << 20, // Set condition code.
|
| lithium-codegen-arm.cc | 843 __ sub(r1, r1, Operand(1), SetCC);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 72 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
522 // Promote all the way up to the canonical SetCC type.
563 // Get the SETCC result using the canonical SETCC type.
564 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
569 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
[all...] |
| DAGCombiner.cpp | 590 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
592 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
597 if (N.getOpcode() == ISD::SETCC) {
615 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 81 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
124 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 setOperationAction(ISD::SETCC, MVT::i64, Custom);
126 setOperationAction(ISD::SETCC, MVT::f32, Custom);
127 setOperationAction(ISD::SETCC, MVT::f64, Custom);
175 setOperationAction(ISD::SETCC, MVT::f128, Custom);
409 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
515 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
[all...] |
