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Searched
defs:TM
(Results
1 - 25
of
137
) sorted by null
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600RegisterInfo.h
27
AMDGPUTargetMachine &
TM
;
30
R600RegisterInfo(AMDGPUTargetMachine &
tm
, const TargetInstrInfo &tii);
SIRegisterInfo.h
27
AMDGPUTargetMachine &
TM
;
30
SIRegisterInfo(AMDGPUTargetMachine &
tm
, const TargetInstrInfo &tii);
AMDGPUConvertToISA.cpp
27
TargetMachine &
TM
;
30
AMDGPUConvertToISAPass(TargetMachine &
tm
) :
31
MachineFunctionPass(ID),
TM
(
tm
) { }
43
FunctionPass *llvm::createAMDGPUConvertToISAPass(TargetMachine &
tm
) {
44
return new AMDGPUConvertToISAPass(
tm
);
50
static_cast<const AMDGPUInstrInfo*>(
TM
.getInstrInfo());
SIInstrInfo.h
26
AMDGPUTargetMachine &
TM
;
29
explicit SIInstrInfo(AMDGPUTargetMachine &
tm
);
AMDGPUInstrInfo.h
43
TargetMachine &
TM
;
47
explicit AMDGPUInstrInfo(TargetMachine &
tm
);
AMDGPURegisterInfo.h
32
TargetMachine &
TM
;
36
AMDGPURegisterInfo(TargetMachine &
tm
, const TargetInstrInfo &tii);
R600InstrInfo.h
35
AMDGPUTargetMachine &
TM
;
40
explicit R600InstrInfo(AMDGPUTargetMachine &
tm
);
63
DFAPacketizer *CreateTargetScheduleState(const TargetMachine *
TM
,
SIAssignInterpRegs.cpp
36
TargetMachine &
TM
;
42
SIAssignInterpRegsPass(TargetMachine &
tm
) :
43
MachineFunctionPass(ID),
TM
(
tm
) { }
63
FunctionPass *llvm::createSIAssignInterpRegsPass(TargetMachine &
tm
) {
64
return new SIAssignInterpRegsPass(
tm
);
126
const TargetInstrInfo * TII =
TM
.getInstrInfo();
/external/mesa3d/src/gallium/drivers/radeon/
R600RegisterInfo.h
27
AMDGPUTargetMachine &
TM
;
30
R600RegisterInfo(AMDGPUTargetMachine &
tm
, const TargetInstrInfo &tii);
SIRegisterInfo.h
27
AMDGPUTargetMachine &
TM
;
30
SIRegisterInfo(AMDGPUTargetMachine &
tm
, const TargetInstrInfo &tii);
AMDGPUConvertToISA.cpp
27
TargetMachine &
TM
;
30
AMDGPUConvertToISAPass(TargetMachine &
tm
) :
31
MachineFunctionPass(ID),
TM
(
tm
) { }
43
FunctionPass *llvm::createAMDGPUConvertToISAPass(TargetMachine &
tm
) {
44
return new AMDGPUConvertToISAPass(
tm
);
50
static_cast<const AMDGPUInstrInfo*>(
TM
.getInstrInfo());
SIInstrInfo.h
26
AMDGPUTargetMachine &
TM
;
29
explicit SIInstrInfo(AMDGPUTargetMachine &
tm
);
AMDGPUInstrInfo.h
43
TargetMachine &
TM
;
47
explicit AMDGPUInstrInfo(TargetMachine &
tm
);
AMDGPURegisterInfo.h
32
TargetMachine &
TM
;
36
AMDGPURegisterInfo(TargetMachine &
tm
, const TargetInstrInfo &tii);
R600InstrInfo.h
35
AMDGPUTargetMachine &
TM
;
40
explicit R600InstrInfo(AMDGPUTargetMachine &
tm
);
63
DFAPacketizer *CreateTargetScheduleState(const TargetMachine *
TM
,
/external/llvm/lib/Target/Mips/
Mips16HardFloat.h
34
TM
(TM_), Subtarget(
TM
.getSubtarget<MipsSubtarget>()) {
46
const TargetMachine &
TM
;
51
ModulePass *createMips16HardFloat(MipsTargetMachine &
TM
);
MipsModuleISelDAGToDAG.h
41
TM
(TM_), Subtarget(
TM
.getSubtarget<MipsSubtarget>()) {}
53
const TargetMachine &
TM
;
59
FunctionPass *createMipsModuleISelDag(MipsTargetMachine &
TM
);
MipsInstrInfo.h
36
MipsTargetMachine &
TM
;
49
explicit MipsInstrInfo(MipsTargetMachine &
TM
, unsigned UncondBrOpc);
51
static const MipsInstrInfo *create(MipsTargetMachine &
TM
);
143
const MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &
TM
);
144
const MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &
TM
);
/external/strace/linux/sparc/
syscallent1.h
143
{ 6, TD|
TM
, solaris_mmap, "mmap" }, /* 115 */
362
{ 6, TI|
TM
, solaris_shmat, "shmat" }, /* 330 */
364
{ 6, TI|
TM
, solaris_shmdt, "shmdt" }, /* 332 */
/external/llvm/include/llvm/CodeGen/
MachineFunctionAnalysis.h
28
const TargetMachine &
TM
;
33
explicit MachineFunctionAnalysis(const TargetMachine &
tm
);
/external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.h
32
const TargetMachine *
TM
;
/external/llvm/lib/Target/AArch64/
AArch64CleanupLocalDynamicTLSPass.cpp
95
const AArch64TargetMachine *
TM
=
97
const AArch64InstrInfo *TII =
TM
->getInstrInfo();
115
const AArch64TargetMachine *
TM
=
117
const AArch64InstrInfo *TII =
TM
->getInstrInfo();
/external/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp
47
const TargetMachine &
TM
=
50
*static_cast<const ARMBaseInstrInfo*>(
TM
.getInstrInfo());
/external/llvm/lib/Target/Hexagon/
HexagonTargetMachine.cpp
81
HexagonPassConfig(HexagonTargetMachine *
TM
, PassManagerBase &PM)
82
: TargetPassConfig(
TM
, PM) {
115
HexagonTargetMachine &
TM
= getHexagonTargetMachine();
119
addPass(createHexagonRemoveExtendArgs(
TM
));
121
addPass(createHexagonISelDag(
TM
, getOptLevel()));
139
const HexagonTargetMachine &
TM
= getHexagonTargetMachine();
142
addPass(createHexagonCFGOptimizer(
TM
));
147
const HexagonTargetMachine &
TM
= getHexagonTargetMachine();
152
addPass(createHexagonSplitConst32AndConst64(
TM
));
158
const HexagonTargetMachine &
TM
= getHexagonTargetMachine()
[
all
...]
/external/llvm/lib/Target/R600/
AMDGPUTargetTransformInfo.cpp
40
const AMDGPUTargetMachine *
TM
;
49
AMDGPUTTI() : ImmutablePass(ID),
TM
(nullptr), ST(nullptr), TLI(nullptr) {
53
AMDGPUTTI(const AMDGPUTargetMachine *
TM
)
54
: ImmutablePass(ID),
TM
(
TM
), ST(
TM
->getSubtargetImpl()),
55
TLI(
TM
->getTargetLowering()) {
90
llvm::createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *
TM
) {
91
return new AMDGPUTTI(
TM
);
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