| /external/llvm/lib/Target/ARM/ |
| ARMFeatures.h | 1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
10 // This file contains the code shared between ARM CodeGen and ARM MC
29 case ARM::tADC:
30 case ARM::tADDi3:
31 case ARM::tADDi8:
32 case ARM::tADDrr:
33 case ARM::tAND:
34 case ARM::tASRri:
35 case ARM::tASRrr
[all...] |
| ARMInstrInfo.cpp | 1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
15 #include "ARM.h"
39 NopInst.setOpcode(ARM::HINT);
44 NopInst.setOpcode(ARM::MOVr);
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
46 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
56 case ARM::LDR_PRE_IMM:
57 case ARM::LDR_PRE_REG:
58 case ARM::LDR_POST_IMM
[all...] |
| ARMExpandPseudoInsts.cpp | 17 #include "ARM.h"
34 #define DEBUG_TYPE "arm-pseudo"
37 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
38 cl::desc("Verify machine code after expanding ARM pseudos"));
54 return "ARM pseudo instruction expansion pass";
135 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
136 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
137 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}
[all...] |
| Thumb2InstrInfo.cpp | 38 NopInst.setOpcode(ARM::tHINT);
80 if (MBBI->getOpcode() == ARM::t2IT) {
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
141 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
142 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
143 RC == &ARM::GPRnopcRegClass) {
144 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12)
[all...] |
| Thumb2SizeReduction.cpp | 10 #include "ARM.h"
62 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
63 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
64 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
65 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 }
[all...] |
| ARMFPUName.h | 1 //===-- ARMFPUName.h - List of the ARM FPU names ----------------*- C++ -*-===//
14 namespace ARM {
23 } // namespace ARM
|
| ARMBaseInstrInfo.cpp | 1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
14 #include "ARM.h"
43 #define DEBUG_TYPE "arm-instrinfo"
49 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
50 cl::desc("Enable ARM 2-addr to 3-addr conv"));
54 cl::desc("Widen ARM vmovs to vmovd when possible"));
73 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }
[all...] |
| ARMCallingConv.h | 1 //=== ARMCallingConv.h - ARM Custom Calling Convention Routines -*- C++ -*-===//
10 // This file contains the custom routines for the ARM Calling Convention that
18 #include "ARM.h"
31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }
[all...] |
| ARMLoadStoreOptimizer.cpp | 1 //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===//
15 #include "ARM.h"
46 #define DEBUG_TYPE "arm-ldst-opt"
79 return "ARM load / store optimization pass";
150 case ARM::LDRi12:
154 case ARM_AM::ia: return ARM::LDMIA;
155 case ARM_AM::da: return ARM::LDMDA;
156 case ARM_AM::db: return ARM::LDMDB;
157 case ARM_AM::ib: return ARM::LDMIB;
159 case ARM::STRi12
[all...] |
| ARMAsmPrinter.cpp | 1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
16 #include "ARM.h"
137 if(ARM::GPRPairRegClass.contains(Reg)) {
140 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
236 if (!ARM::DPRRegClass.contains(*SR))
238 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
263 if (ARM::GPRPairRegClass.contains(RegBegin)) {
265 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
267 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1)
[all...] |
| ARMFrameLowering.cpp | 1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
36 cl::desc("Align ARM NEON spills in prolog and epilog"));
74 // stack frame. ARM (especially Thumb) has small immediate offset to
104 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
105 MI->getOpcode() == ARM::LDR_POST_REG ||
106 MI->getOpcode() == ARM::t2LDR_POST) &&
108 MI->getOperand(1).getReg() == ARM::SP)
135 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes
[all...] |
| ARMBaseRegisterInfo.cpp | 1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
15 #include "ARM.h"
47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), BasePtr(ARM::R6) {
50 FramePtr = ARM::R7;
52 FramePtr = ARM::R11;
54 FramePtr = ARM::R11;
55 else // ARM EAB
[all...] |
| ARMRelocations.h | 1 //===-- ARMRelocations.h - ARM Code Relocations -----------------*- C++ -*-===//
10 // This file defines the ARM target-specific relocation types.
20 namespace ARM {
38 // reloc_arm_machine_cp_entry - Relocation of a ARM machine constantpool
|
| Thumb1InstrInfo.cpp | 29 NopInst.setOpcode(ARM::tMOVr);
30 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
44 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
55 assert((RC == &ARM::tGPRRegClass ||
59 if (RC == &ARM::tGPRRegClass ||
72 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
83 assert((RC == &ARM::tGPRRegClass ||
87 if (RC == &ARM::tGPRRegClass |
[all...] |
| /external/llvm/test/MC/ARM/ |
| big-endian-arm-fixup.s | 8 @ARM::fixup_arm_condbl
15 @ARM::fixup_arm_uncondbl
22 @ARM::fixup_arm_blx
29 @ARM::fixup_arm_uncondbranch
36 @ARM::fixup_arm_condbranch
43 @ARM::fixup_arm_pcrel_10
50 @ARM::fixup_arm_ldst_pcrel_12
57 @ARM::fixup_arm_adr_pcrel_12
64 @ARM::fixup_arm_adr_pcrel_10_unscaled
71 @ARM::fixup_arm_movw_lo1
[all...] |
| big-endian-thumb-fixup.s | 8 @ARM::fixup_arm_thumb_bl
16 @ARM::fixup_arm_thumb_blx
23 @ARM::fixup_arm_thumb_br
31 @ARM::fixup_arm_thumb_bcc
39 @ARM::fixup_arm_thumb_cb
47 @ARM::fixup_arm_thumb_cp
56 @ARM::fixup_arm_thumb_adr_pcrel_10
|
| big-endian-thumb2-fixup.s | 7 @ARM::fixup_t2_movw_lo16
13 @ARM::fixup_t2_movt_hi16
20 @ARM::fixup_t2_uncondbranch
28 @ARM::fixup_t2_condbranch
36 @ARM::fixup_t2_ldst_precel_12
43 @ARM::fixup_t2_adr_pcrel_12
|
| invalid-idiv.s | 1 @ RUN: not llvm-mc -triple=armv7 -mcpu=cortex-a15 -mattr=-hwdiv-arm < %s 2> %t
2 @ RUN: FileCheck --check-prefix=ARM-A15 < %t %s
6 @ RUN: FileCheck --check-prefix=ARM < %t %s
12 @ ARM-A15: error: instruction requires: divide in ARM
13 @ ARM-A15: sdiv r1, r2, r3
14 @ ARM-A15: error: instruction requires: divide in ARM
15 @ ARM-A15: udiv r3, r4, r5
16 @ THUMB-A15: error: instruction requires: arm-mod
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMELFObjectWriter.cpp | 1 //===-- ARMELFObjectWriter.cpp - ARM ELF Writer ---------------------------===//
99 case ARM::fixup_arm_blx:
100 case ARM::fixup_arm_uncondbl:
113 case ARM::fixup_arm_condbl:
114 case ARM::fixup_arm_condbranch:
115 case ARM::fixup_arm_uncondbranch:
118 case ARM::fixup_t2_condbranch:
119 case ARM::fixup_t2_uncondbranch:
122 case ARM::fixup_arm_movt_hi16:
125 case ARM::fixup_arm_movw_lo16
[all...] |
| ARMAsmBackend.cpp | 1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
56 return ARM::NumTargetFixupKinds;
60 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
64 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
101 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
190 case ARM::tBcc: return ARM::t2Bcc;
191 case ARM::tLDRpci: return ARM::t2LDRpci;
192 case ARM::tADR: return ARM::t2ADR
[all...] |
| ARMWinCOFFObjectWriter.cpp | 1 //===-- ARMWinCOFFObjectWriter.cpp - ARM Windows COFF Object Writer -- C++ -==//
58 case ARM::fixup_t2_condbranch:
60 case ARM::fixup_t2_uncondbranch:
62 case ARM::fixup_arm_thumb_bl:
63 case ARM::fixup_arm_thumb_blx:
65 case ARM::fixup_t2_movw_lo16:
66 case ARM::fixup_t2_movt_hi16:
72 return static_cast<unsigned>(Fixup.getKind()) != ARM::fixup_t2_movt_hi16;
|
| ARMArchName.h | 1 //===-- ARMArchName.h - List of the ARM arch names --------------*- C++ -*-===//
14 namespace ARM {
24 } // namespace ARM
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
30 #define DEBUG_TYPE "arm-disassembler"
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
424 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
425 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
447 // VFP and NEON instructions, similarly, are shared between ARM
570 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
572 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
577 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR))
[all...] |
| /external/lzma/CPP/7zip/ |
| Aes.mak | 4 !IF "$(CPU)" != "IA64" && "$(CPU)" != "MIPS" && "$(CPU)" != "ARM"
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
71 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
126 FPReg = ARM::SP;
242 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
245 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
248 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
251 return STI.getFeatureBits() & ARM::HasV4TOps;
254 return STI.getFeatureBits() & ARM::HasV6Ops;
257 return STI.getFeatureBits() & ARM::HasV6MOps;
260 return STI.getFeatureBits() & ARM::HasV7Ops
[all...] |
