/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 52 /// AssertSext, AssertZext - These nodes record if a register contains a 57 AssertSext, AssertZext, [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGDumper.cpp | 78 case ISD::AssertSext: return "AssertSext";
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LegalizeIntegerTypes.cpp | 53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 160 return DAG.getNode(ISD::AssertSext, SDLoc(N), 401 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, [all...] |
SelectionDAGBuilder.cpp | 101 /// (ISD::AssertSext). 236 /// ValueVT (ISD::AssertSext). 722 // now, just use the tightest assertzext/assertsext possible. 746 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, [all...] |
SelectionDAGISel.cpp | [all...] |
SelectionDAG.cpp | [all...] |
DAGCombiner.cpp | [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | 410 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 579 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 473 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 631 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |