| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 52 /// AssertSext, AssertZext - These nodes record if a register contains a
57 AssertSext, AssertZext,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 79 case ISD::AssertZext: return "AssertZext";
|
| LegalizeIntegerTypes.cpp | 54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
167 return DAG.getNode(ISD::AssertZext, SDLoc(N),
401 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
411 return DAG.getNode(ISD::AssertZext, dl,
[all...] |
| TargetLowering.cpp | [all...] |
| SelectionDAGBuilder.cpp | 100 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
235 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
722 // now, just use the tightest assertzext/assertsext possible.
746 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
[all...] |
| SelectionDAG.cpp | [all...] |
| SelectionDAGISel.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 476 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 583 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 634 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
