/external/libhevc/decoder/arm/ |
ihevcd_fmt_conv_420sp_to_rgba8888.s | 227 VQMOVUN.S16 D15,Q9 231 VZIP.8 D14,D15 249 VST1.32 D15,[R2]! 278 VQMOVUN.S16 D15,Q9 282 VZIP.8 D14,D15 300 VST1.32 D15,[R8]! 358 VQMOVUN.S16 D15,Q9 362 VZIP.8 D14,D15 380 VST1.32 D15,[R2]! 400 VQMOVUN.S16 D15,Q [all...] |
/art/compiler/utils/mips/ |
constants_mips.h | 47 D15 = 15,
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/frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
pred_lt4_1_neon.s | 68 VQDMLAL.S16 Q15, D15, D7 85 VEXT.S16 D14, D14, D15, #1 88 VEXT.S16 D15, D15, D24, #1
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Filt_6k_7k_neon.s | 118 VMLAL.S16 Q10,D15,D7[0] 119 VMLAL.S16 Q11,D15,D6[0] 140 VMLAL.S16 Q10,D15,D7[1] 141 VMLAL.S16 Q11,D15,D6[1] 162 VMLAL.S16 Q10,D15,D7[2] 163 VMLAL.S16 Q11,D15,D6[2] 184 VMLAL.S16 Q10,D15,D7[3] 185 VMLAL.S16 Q11,D15,D6[3] 199 VMOV.S16 D14,D15 201 VMOV.S16 D15,D1 [all...] |
Dot_p_neon.s | 63 VMLAL.S16 Q15, D3, D15 95 VMLAL.S16 Q15, D15, D15
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Norm_Corr_neon.s | 93 VMLAL.S16 Q10, D15, D15 135 VMLAL.S16 Q11, D7, D15 156 VMLAL.S16 Q11, D7, D15
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scale_sig_neon.s | 118 VSHLL.S16 Q13, D15, #16
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/external/llvm/test/MC/MachO/ |
x86_32-symbols.s | 50 D15: 821 // CHECK: ('_string', 'D15')
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/art/compiler/utils/arm/ |
managed_register_arm_test.cc | 174 reg = ArmManagedRegister::FromDRegister(D15); 181 EXPECT_EQ(D15, reg.AsDRegister()); 366 ArmManagedRegister reg_D15 = ArmManagedRegister::FromDRegister(D15); 374 EXPECT_TRUE(reg_D15.Equals(ArmManagedRegister::FromDRegister(D15))); 386 EXPECT_TRUE(!reg_D16.Equals(ArmManagedRegister::FromDRegister(D15))); 398 EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::FromDRegister(D15))); 411 EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromDRegister(D15))); 426 EXPECT_TRUE(!reg_R0R1.Equals(ArmManagedRegister::FromDRegister(D15))); 438 EXPECT_TRUE(!reg_R4R5.Equals(ArmManagedRegister::FromDRegister(D15))); 451 EXPECT_TRUE(!reg_R6R7.Equals(ArmManagedRegister::FromDRegister(D15))); [all...] |
constants_arm.h | 75 D15 = 15,
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/external/libhevc/common/arm/ |
ihevc_sao_edge_offset_class0_chroma.s | 153 VMOV.16 D15[3],r11 @vsetq_lane_u16(pu1_src_left[ht - row], pu1_cur_row_tmp, 14,15) 207 VTBL.8 D15,{D10},D15 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx)) 211 VUZP.8 D14,D15 218 VTBL.8 D17,{D0},D15 241 VMOVN.I16 D15,Q6 @vmovn_s16(pi2_tmp_cur_row.val[1]) 261 VST1.8 {D14,D15},[r12],r1 @vst1q_u8(pu1_src_cpy, pu1_cur_row) 316 VMOV.16 D15[3],r11 @vsetq_lane_u8(pu1_src_left[ht - row], pu1_cur_row_tmp, 15) 372 VTBL.8 D15,{D10},D15 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx) [all...] |
ihevc_sao_band_offset_chroma.s | 176 VCLE.U8 D15,D2,D30 @vcle_u8(band_table.val[1], vdup_n_u8(16)) 178 VORR.U8 D2,D2,D15 @band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp) 189 VAND.U8 D2,D2,D15 @band_table.val[1] = vand_u8(band_table.val[1], au1_cmp) 210 VADD.I8 D15,D11,D30 @band_table_v.val[2] = vadd_u8(band_table_v.val[2], band_pos_v) 222 VADD.I8 D11,D15,D27 @band_table_v.val[2] = vadd_u8(band_table_v.val[2], vdup_n_u8(pi1_sao_offset_v[3])) 296 VSUB.I8 D15,D13,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u) 304 VTBX.8 D13,{D1-D4},D15 @vtbx4_u8(au1_cur_row_deint.val[0], band_table_u, vsub_u8(au1_cur_row_deint.val[0], band_pos_u)) 350 VSUB.I8 D15,D13,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u) 358 VTBX.8 D13,{D1-D4},D15 @vtbx4_u8(au1_cur_row_deint.val[0], band_table_u, vsub_u8(au1_cur_row_deint.val[0], band_pos_u))
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ihevc_sao_band_offset_luma.s | 195 VLD1.8 D15,[r5] @au1_cur_row = vld1_u8(pu1_src_cpy) 203 VSUB.I8 D16,D15,D31 @vsub_u8(au1_cur_row, band_pos) 205 VTBX.8 D15,{D1-D4},D16 @vtbx4_u8(au1_cur_row, band_table, vsub_u8(au1_cur_row, band_pos)) 214 VST1.8 D15,[r5] @vst1_u8(pu1_src_cpy, au1_cur_row)
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ihevc_sao_edge_offset_class0.s | 147 VMOV.8 D15[7],r11 @vsetq_lane_u8(pu1_src_left[ht - row], pu1_cur_row_tmp, 15) 206 VTBL.8 D15,{D10},D15 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx)) 224 VTBL.8 D17,{D11},D15 @offset = vtbl1_s8(offset_tbl, vget_high_s8(edge_idx)) 294 VMOV.8 D15[7],r11 @vsetq_lane_u8(pu1_src_left[ht - row], pu1_cur_row_tmp, 15)
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ihevc_sao_edge_offset_class3_chroma.s | 386 VMOV.8 D15[6],r8 @I sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[14] -pu1_src_cpy[16 - src_strd]), sign_up, 0) 389 VMOV.8 D15[7],r9 @I sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] -pu1_src_cpy[17 - src_strd]), sign_up, 1) 467 VMOV.8 D15[6],r10 @II sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[14] -pu1_src_cpy[16 - src_strd]), sign_up, 0) 472 VMOV.8 D15[7],r8 @II sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] -pu1_src_cpy[17 - src_strd]), sign_up, 1) 518 VMOV.8 D15[6],r9 @III sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[14] -pu1_src_cpy[16 - src_strd]), sign_up, 0) 521 VMOV.8 D15[7],r10 @III sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] -pu1_src_cpy[17 - src_strd]), sign_up, 1) 622 VMOV.8 D15[6],r8 @sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[14] -pu1_src_cpy[16 - src_strd]), sign_up, 0) 626 VMOV.8 D15[7],r10 @sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] -pu1_src_cpy[17 - src_strd]), sign_up, 1) [all...] |
/art/compiler/utils/arm64/ |
managed_register_arm64_test.cc | 374 Arm64ManagedRegister reg_D15 = Arm64ManagedRegister::FromDRegister(D15); 383 EXPECT_TRUE(reg_D15.Equals(Arm64ManagedRegister::FromDRegister(D15))); 407 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); 429 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); 451 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); 475 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); 497 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); 518 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); 539 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); 563 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); [all...] |
/art/runtime/arch/arm64/ |
registers_arm64.h | 130 D15 = 15,
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quick_method_frame_info_arm64.h | 60 (1 << art::arm64::D14) | (1 << art::arm64::D15);
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/external/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.h | 67 case D15: case D14: case D13: case D12:
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/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
armVCM4P10_DeblockingChroma_unsafe_s.s | 55 dMask_1 DN D15.U8 168 ;// - Additional Params - alpha: D0, dMask_1: D15
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omxVCM4P10_FilterDeblockingChroma_HorEdge_I_s.s | 72 dMask_1 DN D15.U8 89 M_START omxVCM4P10_FilterDeblockingChroma_HorEdge_I, r9, d15
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/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S | 86 #define dXi7 D15.F32 174 #define dT1 D15.F32
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armSP_FFT_CToC_SC16_Radix4_ls_unsafe_s.S | 121 #define dTmp3S32 D15.S32 130 #define dYi3 D15.S16
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armSP_FFT_CToC_FC32_Radix4_fs_unsafe_s.S | 86 #define dYi3 D15.F32
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armSP_FFT_CToC_SC16_Radix4_fs_unsafe_s.S | 94 #define dYi3 D15.S16
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