/external/chromium_org/v8/test/cctest/ |
test-assembler-mips.cc | 1148 // Save FCSR. 1149 __ cfc1(a1, FCSR); 1151 __ ctc1(zero_reg, FCSR); 1170 __ ctc1(zero_reg, FCSR); \ 1172 __ cfc1(a2, FCSR); \ 1176 __ ctc1(zero_reg, FCSR); \ 1178 __ cfc1(a2, FCSR); \ 1182 __ ctc1(zero_reg, FCSR); \ 1184 __ cfc1(a2, FCSR); \ 1188 __ ctc1(zero_reg, FCSR); \ [all...] |
/external/valgrind/main/VEX/priv/ |
host_mips_defs.h | 152 #define FCSR() hregMIPS_FCSR() 341 Min_MtFCSR, /* set FCSR register */ 342 Min_MfFCSR, /* get FCSR register */ 597 /* Move from GP register to FCSR register. */ 601 /* Move from FCSR register to GP register. */
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/external/chromium_org/v8/src/mips/ |
macro-assembler-mips.cc | [all...] |
assembler-mips.h | 333 // Currently only FCSR (#31) is implemented. 354 const FPUControlRegister FCSR = { kFCSRRegister }; [all...] |
code-stubs-mips.cc | 616 // Clear cumulative exception flags and save the FCSR. 617 __ cfc1(scratch2, FCSR); 618 __ ctc1(zero_reg, FCSR); 625 // Retrieve and restore the FCSR. 626 __ cfc1(scratch, FCSR); 627 __ ctc1(scratch2, FCSR); [all...] |
/external/valgrind/main/memcheck/ |
mc_machine.c | [all...] |
/external/valgrind/main/none/tests/mips32/ |
round.stdout.exp | 3 fcsr: 0x0 5 fcsr: 0x1004 7 fcsr: 0x0 9 fcsr: 0x0 11 fcsr: 0x1004 13 fcsr: 0x1004 15 fcsr: 0x0 17 fcsr: 0x1004 19 fcsr: 0x0 21 fcsr: 0x100 [all...] |
round_fpu64.stdout.exp | 1 -------------------------- test FPU Conversion Operations Using the FCSR Rounding Mode -------------------------- 4 fcsr: 0x0 6 fcsr: 0x1004 8 fcsr: 0x0 10 fcsr: 0x0 12 fcsr: 0x1004 14 fcsr: 0x1004 16 fcsr: 0x0 18 fcsr: 0x1004 20 fcsr: 0x [all...] |
/external/robolectric/lib/main/ |
sqlite-jdbc-3.7.2.jar | |
/external/valgrind/main/none/tests/mips64/ |
round.stdout.exp | 3 fcsr: 0x0 5 fcsr: 0x1004 7 fcsr: 0x4 9 fcsr: 0x4 11 fcsr: 0x1004 13 fcsr: 0x1004 15 fcsr: 0x4 17 fcsr: 0x1004 19 fcsr: 0x4 21 fcsr: 0x100 [all...] |