| /external/llvm/include/llvm/MC/MCAnalysis/ |
| MCModuleYAML.h | 31 const MCInstrInfo &MII, const MCRegisterInfo &MRI);
36 const MCInstrInfo &MII, const MCRegisterInfo &MRI);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 65 MachineRegisterInfo *MRI;
101 const MachineRegisterInfo *MRI) {
105 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
110 const MachineRegisterInfo *MRI) {
112 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
114 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
124 const MachineRegisterInfo *MRI,
141 MRI) &&
142 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
145 MRI) &
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRCopies.cpp | 88 const MachineRegisterInfo &MRI,
92 const MachineRegisterInfo &MRI,
96 const MachineRegisterInfo &MRI) const;
118 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
124 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
135 const MachineRegisterInfo &MRI,
143 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
146 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) {
149 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
[all...] |
| SIMachineFunctionInfo.cpp | 32 static unsigned createLaneVGPR(MachineRegisterInfo &MRI, MachineFunction *MF) {
33 unsigned VGPR = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
73 MachineRegisterInfo &MRI, MachineFunction *MF, unsigned NumRegs) {
77 LaneVGPR = createLaneVGPR(MRI, MF);
81 LaneVGPR = createLaneVGPR(MRI, MF);
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| AMDGPUMCTargetDesc.h | 35 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,
43 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
| AMDGPUMCTargetDesc.cpp | 69 const MCRegisterInfo &MRI,
71 return new AMDGPUInstPrinter(MAI, MII, MRI);
75 const MCRegisterInfo &MRI,
79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
81 return createR600MCCodeEmitter(MCII, MRI, STI);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo();
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg))
[all...] |
| SIISelLowering.h | 33 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
35 MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const;
37 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
39 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo();
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg))
[all...] |
| SIISelLowering.h | 33 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
35 MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const;
37 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
39 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCTargetDesc.h | 37 const MCRegisterInfo &MRI,
41 const MCRegisterInfo &MRI,
46 const MCRegisterInfo &MRI, StringRef TT,
49 const MCRegisterInfo &MRI, StringRef TT,
52 const MCRegisterInfo &MRI, StringRef TT,
55 const MCRegisterInfo &MRI, StringRef TT,
|
| /external/llvm/lib/CodeGen/ |
| RegAllocBase.cpp | 61 MRI = &vrm.getRegInfo();
65 MRI->freezeReservedRegs(vrm.getMachineFunction());
74 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
76 if (MRI->reg_nodbg_empty(Reg))
92 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
105 << MRI->getRegClass(VirtReg->reg)->getName()
116 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
130 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
141 if (MRI->reg_nodbg_empty(SplitVirtReg->reg))
[all...] |
| OptimizePHIs.cpp | 32 MachineRegisterInfo *MRI;
68 MRI = &Fn.getRegInfo();
106 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
113 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
146 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
170 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
173 MRI->replaceRegWith(OldReg, SingleValReg);
|
| PHIEliminationUtils.cpp | 36 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
37 for (MachineInstr &RI : MRI.reg_instructions(SrcReg)) {
|
| RegAllocBase.h | 62 MachineRegisterInfo *MRI;
69 : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.h | 38 const MCRegisterInfo &MRI,
42 const MCRegisterInfo &MRI, StringRef TT,
45 const MCRegisterInfo &MRI, StringRef TT,
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/InstPrinter/ |
| AMDGPUInstPrinter.h | 14 const MCRegisterInfo &MRI)
15 : MCInstPrinter(MAI, MII, MRI) {}
|
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCTargetDesc.h | 35 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,
|
| /external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
| AMDGPUInstPrinter.h | 14 const MCRegisterInfo &MRI)
15 : MCInstPrinter(MAI, MII, MRI) {}
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.h | 57 const MCRegisterInfo &MRI,
62 const MCRegisterInfo &MRI,
66 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
70 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
73 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
76 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
79 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.h | 25 const MCRegisterInfo &MRI)
26 : MCInstPrinter(MAI, MII, MRI) {}
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.h | 39 const MCRegisterInfo &MRI,
43 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCTargetDesc.h | 73 const MCRegisterInfo &MRI,
78 const MCRegisterInfo &MRI,
|
| /external/llvm/lib/Target/XCore/InstPrinter/ |
| XCoreInstPrinter.h | 27 const MCRegisterInfo &MRI)
28 : MCInstPrinter(MAI, MII, MRI) {}
|
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 112 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
113 unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);
126 unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
127 unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
191 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
195 if (MRI->isPhysRegUsed(reg))
199 if (MRI->isPhysRegUsed(reg))
208 MachineRegisterInfo &MRI = MF.getRegInfo();
212 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
213 || MRI.isPhysRegUsed(SP::O6) // %SP is use
[all...] |
