| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 115 case MVT::i1: return "i1";
116 case MVT::i8: return "i8";
117 case MVT::i16: return "i16";
118 case MVT::i32: return "i32";
119 case MVT::i64: return "i64";
120 case MVT::i128: return "i128";
121 case MVT::f16: return "f16";
122 case MVT::f32: return "f32";
123 case MVT::f64: return "f64";
124 case MVT::f80: return "f80"
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 25 /// MVT - Machine Value Type. Every type that is supported natively by some
27 /// type can be represented by an MVT.
28 class MVT {
124 // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
158 MVT() : SimpleTy((SimpleValueType)(INVALID_SIMPLE_VALUE_TYPE)) {}
159 MVT(SimpleValueType SVT) : SimpleTy(SVT) { }
161 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
162 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
163 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
164 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy;
[all...] |
| ValueTypes.h | 30 /// a MVT can represent.
33 MVT V;
37 EVT() : V((MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE)),
39 EVT(MVT::SimpleValueType SVT) : V(SVT), LLVMTy(nullptr) { }
40 EVT(MVT S) : V(S), LLVMTy(nullptr) {}
57 return MVT::getFloatingPointVT(BitWidth);
63 MVT M = MVT::getIntegerVT(BitWidth);
72 MVT M = MVT::getVectorVT(VT.V, NumElements)
[all...] |
| FastISel.h | 31 class MVT;
184 virtual unsigned FastEmit_(MVT VT,
185 MVT RetVT,
190 virtual unsigned FastEmit_r(MVT VT,
191 MVT RetVT,
197 virtual unsigned FastEmit_rr(MVT VT,
198 MVT RetVT,
206 virtual unsigned FastEmit_ri(MVT VT,
207 MVT RetVT,
215 virtual unsigned FastEmit_rf(MVT VT
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 189 static const CostTblEntry<MVT::SimpleValueType> NEONFltDblTbl[] = {
191 { ISD::FP_ROUND, MVT::v2f64, 2 },
192 { ISD::FP_EXTEND, MVT::v2f32, 2 },
193 { ISD::FP_EXTEND, MVT::v4f32, 4 }
198 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
213 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
215 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
216 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }
[all...] |
| ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32;
68 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
69 DAG.getConstant(SrcOff, MVT::i32)),
75 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
81 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
82 DAG.getConstant(DstOff, MVT::i32)),
87 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
101 VT = MVT::i16;
104 VT = MVT::i8;
109 DAG.getNode(ISD::ADD, dl, MVT::i32, Src
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CallingConv.h | 23 inline bool CC_X86_AnyReg_Error(unsigned &, MVT &, MVT &,
|
| X86TargetTransformInfo.cpp | 185 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
190 static const CostTblEntry<MVT::SimpleValueType>
192 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
193 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
194 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
195 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
205 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTable[] = {
208 { ISD::SHL, MVT::v4i32, 1 },
209 { ISD::SRL, MVT::v4i32, 1 },
210 { ISD::SRA, MVT::v4i32, 1 }
[all...] |
| X86ISelLowering.cpp | 241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote)
[all...] |
| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 25 class MVT;
39 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
41 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
43 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
45 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
50 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
55 void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
60 void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
63 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 250 Val = CurDAG->getTargetConstant(Immed, MVT::i32);
251 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
276 if (N.getValueType() == MVT::i32)
284 return SelectArithImmed(CurDAG->getConstant(Immed, MVT::i32), Val, Shift);
332 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
351 if (!IsLoadStore && SrcVT == MVT::i8)
353 else if (!IsLoadStore && SrcVT == MVT::i16)
355 else if (SrcVT == MVT::i32)
357 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
363 if (!IsLoadStore && SrcVT == MVT::i8
[all...] |
| AArch64TargetTransformInfo.cpp | 306 static const TypeConversionCostTblEntry<MVT> ConversionTbl[] = {
308 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
309 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
310 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
311 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
312 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 421 if (OpVT == MVT::f32) {
422 if (RetVT == MVT::f64)
424 if (RetVT == MVT::f128)
426 } else if (OpVT == MVT::f64) {
427 if (RetVT == MVT::f128)
437 if (RetVT == MVT::f32) {
438 if (OpVT == MVT::f64)
440 if (OpVT == MVT::f80)
442 if (OpVT == MVT::f128)
444 if (OpVT == MVT::ppcf128
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 36 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
38 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
39 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
42 std::string llvm::getName(MVT::SimpleValueType T) {
44 case MVT::Other: return "UNKNOWN";
45 case MVT::iPTR: return "TLI.getPointerTy()";
46 case MVT::iPTRAny: return "TLI.getPointerTy()";
51 std::string llvm::getEnumName(MVT::SimpleValueType T) {
53 case MVT::Other: return "MVT::Other"
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 51 (int)MVT::i8,
52 (int)MVT::i16,
53 (int)MVT::i32,
54 (int)MVT::f32,
55 (int)MVT::f64,
56 (int)MVT::i64,
57 (int)MVT::v2i8,
58 (int)MVT::v4i8,
59 (int)MVT::v2i16,
60 (int)MVT::v4i16
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 51 (int)MVT::i8,
52 (int)MVT::i16,
53 (int)MVT::i32,
54 (int)MVT::f32,
55 (int)MVT::f64,
56 (int)MVT::i64,
57 (int)MVT::v2i8,
58 (int)MVT::v4i8,
59 (int)MVT::v2i16,
60 (int)MVT::v4i16
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 65 CC_Hexagon(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 CC_Hexagon32(unsigned ValNo, MVT ValVT,
71 MVT LocVT, CCValAssign::LocInfo LocInfo,
75 CC_Hexagon64(unsigned ValNo, MVT ValVT,
76 MVT LocVT, CCValAssign::LocInfo LocInfo,
80 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
81 MVT LocVT, CCValAssign::LocInfo LocInfo,
85 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
86 MVT LocVT, CCValAssign::LocInfo LocInfo
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 329 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
418 MVT SimpleVT = LoadedVT.getSimpleVT();
436 MVT ScalarVT = SimpleVT.getScalarType();
453 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
457 case MVT::i8:
460 case MVT::i16:
463 case MVT::i32:
466 case MVT::i64:
469 case MVT::f32:
472 case MVT::f64
[all...] |
| NVPTXISelLowering.cpp | 51 static bool IsPTXVectorType(MVT VT) {
55 case MVT::v2i1:
56 case MVT::v4i1:
57 case MVT::v2i8:
58 case MVT::v4i8:
59 case MVT::v2i16:
60 case MVT::v4i16:
61 case MVT::v2i32:
62 case MVT::v4i32:
63 case MVT::v2i64
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 83 return CurDAG->getTargetConstant(Imm, MVT::i32);
89 return CurDAG->getTargetConstant(Imm, MVT::i64);
277 if (PPCLowering->getPointerTy() == MVT::i32) {
300 if (N->getValueType(0) == MVT::i32)
314 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
324 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
375 if (N->getValueType(0) != MVT::i32)
484 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
497 if (LHS.getValueType() == MVT::i32) {
503 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS
[all...] |
| PPCFastISel.cpp | 110 unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
141 bool isTypeLegal(Type *Ty, MVT &VT);
142 bool isLoadTypeLegal(Type *Ty, MVT &VT);
145 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
148 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
150 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
152 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
154 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 33 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
34 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
36 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
37 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
39 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
40 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
42 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
43 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
44 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
46 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 76 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
93 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
94 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
95 setOperationAction(ISD::ADDC, MVT::i32, Expand);
96 setOperationAction(ISD::ADDE, MVT::i32, Expand);
97 setOperationAction(ISD::SUBC, MVT::i32, Expand);
98 setOperationAction(ISD::SUBE, MVT::i32, Expand);
101 setOperationAction(ISD::ADD, MVT::i64, Custom);
102 setOperationAction(ISD::SUB, MVT::i64, Custom);
103 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom)
[all...] |
| XCoreISelDAGToDAG.cpp | 53 return CurDAG->getTargetConstant(Imm, MVT::i32);
94 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
95 Offset = CurDAG->getTargetConstant(0, MVT::i32);
104 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
105 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
122 Reg = CurDAG->getRegister(XCore::CP, MVT::i32);
125 Reg = CurDAG->getRegister(XCore::DP, MVT::i32);
145 MVT::i32, MskSize);
152 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
153 MVT::Other, CPIdx
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 72 bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
74 bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
80 bool isTypeLegal(Type *Ty, MVT &VT);
81 bool isLoadTypeLegal(Type *Ty, MVT &VT);
83 unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
84 unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
85 unsigned MaterializeInt(const Constant *C, MVT VT);
119 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
122 if (evt == MVT::Other || !evt.isSimple())
131 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT)
[all...] |
