| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 98 const MemOpQueue &MemOps, unsigned DefReg,
111 MemOpQueue &MemOps,
127 unsigned Scratch, MemOpQueue &MemOps,
129 void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
560 /// uses we find is a kill. Unfortunately MemOps is not sorted by Position, so
563 SmallVectorImpl<MachineOperand *> &UsesOfImpDefs, const MemOpQueue &MemOps,
572 for (unsigned i = 0; i < MemOps.size(); ++i) {
573 MachineInstr &MI = *MemOps[i].MBBI;
574 unsigned MIPosition = MemOps[i].Position;
608 // MergeOpsUpdate - call MergeOps and update MemOps and merges accordingly o
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 858 SmallVector<SDValue, 4> MemOps;
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 762 SDValue MemOps[SystemZ::NumArgFPRs];
770 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
777 makeArrayRef(&MemOps[NumFixedFPRs],
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
