| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target.h | 139 struct OpInfo
141 OpInfo *variants;
161 inline const OpInfo& getOpInfo(const Instruction *) const;
162 inline const OpInfo& getOpInfo(const operation) const;
210 OpInfo opInfo[OP_LAST + 1];
213 const Target::OpInfo& Target::getOpInfo(const Instruction *insn) const
215 return opInfo[MIN2(insn->op, OP_LAST)];
218 const Target::OpInfo& Target::getOpInfo(const operation op) const
220 return opInfo[op]
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target.h | 139 struct OpInfo
141 OpInfo *variants;
161 inline const OpInfo& getOpInfo(const Instruction *) const;
162 inline const OpInfo& getOpInfo(const operation) const;
210 OpInfo opInfo[OP_LAST + 1];
213 const Target::OpInfo& Target::getOpInfo(const Instruction *insn) const
215 return opInfo[MIN2(insn->op, OP_LAST)];
218 const Target::OpInfo& Target::getOpInfo(const operation op) const
220 return opInfo[op]
[all...] |
| /external/llvm/include/llvm/Bitcode/ |
| BitCodes.h | 181 void Add(const BitCodeAbbrevOp &OpInfo) {
182 OperandList.push_back(OpInfo);
|
| /external/llvm/utils/TableGen/ |
| AsmWriterInst.cpp | 172 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo];
174 unsigned MIOp = OpInfo.MIOperandNo;
175 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName,
|
| AsmMatcherEmitter.cpp | [all...] |
| FixedLenDecoderEmitter.cpp | 457 const OperandInfo &OpInfo) const;
[all...] |
| InstrInfoEmitter.cpp | 58 const OperandInfoMapTy &OpInfo,
464 const OperandInfoMapTy &OpInfo,
541 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
|
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 148 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
159 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
161 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
586 if (OpInfo[i].isPredicate())
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGExprComplex.cpp | 644 BinOpInfo OpInfo;
649 OpInfo.Ty = E->getComputationResultType();
652 assert(OpInfo.Ty->isAnyComplexType());
653 assert(CGF.getContext().hasSameUnqualifiedType(OpInfo.Ty,
655 OpInfo.RHS = Visit(E->getRHS());
662 OpInfo.LHS = EmitComplexToComplexCast(LHSVal, LHSTy, OpInfo.Ty);
665 OpInfo.LHS = EmitScalarToComplexCast(LHSVal, LHSTy, OpInfo.Ty);
669 ComplexPairTy Result = (this->*Func)(OpInfo);
[all...] |
| CGExprScalar.cpp | [all...] |
| /external/lldb/source/Plugins/Disassembler/llvm/ |
| DisassemblerLLVMC.h | 118 int OpInfo(uint64_t PC,
|
| DisassemblerLLVMC.cpp | 769 return static_cast<DisassemblerLLVMC*>(disassembler)->OpInfo (pc,
788 int DisassemblerLLVMC::OpInfo (uint64_t PC,
|
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 124 TargetTransformInfo::OperandValueKind OpInfo =
129 OpInfo = TargetTransformInfo::OK_NonUniformConstantValue;
131 OpInfo = TargetTransformInfo::OK_UniformConstantValue;
134 return OpInfo;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 98 switch (MI.getDesc().OpInfo[i].RegClass) {
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 79 unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 728 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
730 if (SkipPred && MCID.OpInfo[i].isPredicate())
764 if (MCID.OpInfo[i].isPredicate())
774 !MCID.OpInfo[i].isPredicate()) {
824 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
834 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
[all...] |
| ARMCodeEmitter.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 213 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
|
| CodeGenPrepare.cpp | [all...] |
| TargetInstrInfo.cpp | 48 short RegClass = MCID.OpInfo[OpNum].RegClass;
49 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
226 if (MCID.OpInfo[i].isPredicate()) {
|
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 561 switch (Desc.OpInfo[i].OperandType) {
563 int RegClass = Desc.OpInfo[i].RegClass;
584 int RegClass = Desc.OpInfo[i].RegClass;
739 Desc.OpInfo[OpNo].RegClass == -1)
742 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
762 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 253 switch (MI->getDesc().OpInfo->RegClass) {
|
