| /external/llvm/utils/TableGen/ |
| AsmWriterInst.h | 11 // the string into operands, which can be literal strings (the constant bits of
12 // the string), actual operands (i.e., operands from the MachineInstr), and
87 std::vector<AsmWriterOperand> Operands;
103 if (!Operands.empty() &&
104 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
105 Operands.back().Str.append(Str);
107 Operands.push_back(AsmWriterOperand(Str));
|
| FastISelEmitter.cpp | 72 /// types. It has utility methods for emitting text based on the operands.
116 SmallVector<OpKind, 3> Operands;
119 return Operands < O.Operands;
122 return Operands == O.Operands;
125 bool empty() const { return Operands.empty(); }
128 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
129 if (Operands[i].isImm() && Operands[i].getImmCode() != 0
[all...] |
| AsmWriterInst.cpp | 165 Operands.push_back(AsmWriterOperand("PrintSpecial",
171 unsigned OpNo = CGI.Operands.getOperandNamed(VarName);
172 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo];
175 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName,
182 Operands.push_back(AsmWriterOperand("return;",
191 if (Operands.size() != Other.Operands.size()) return ~1;
194 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
195 if (Operands[i] != Other.Operands[i])
[all...] |
| PseudoLoweringEmitter.cpp | 89 // Normal operands should always have the same type, or we have a
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
97 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
101 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
103 OpsAdded += Insn.Operands[i].MINumOperands;
109 // Just add the operands recursively. This is almost certainly
146 if (Insn.Operands.size() != Dag->getNumArgs())
151 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
152 NumMIOperands += Insn.Operands[i].MINumOperands;
158 // If there are more operands that weren't in the DAG, they have t
[all...] |
| InstrInfoEmitter.cpp | 64 std::map<std::string, unsigned> &Operands,
91 for (auto &Op : Inst.Operands) {
92 // Handle aggregate operands and normal operands the same way by expanding
93 // either case into a list of operands for this op.
97 // registers in their multi-operand operands. It may also be an anonymous
135 // Predicate operands. Check to see if the original unexpanded operand
140 // Optional def operands. Check to see if the original unexpanded operand
196 /// \param Operands [out] A map used to generate the OpName enum with operand
204 std::map<std::string, unsigned> &Operands,
[all...] |
| CodeEmitterGen.cpp | 93 // operand number. Non-matching operands are assumed to be in
96 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
98 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
99 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
102 unsigned NumberOps = CGI.Operands.size();
106 (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) ||
108 CGI.Operands.getSubOperandNumber(NumberedOp).first)))) {
111 if (NumberedOp >= CGI.Operands.back().MIOperandNo +
112 CGI.Operands.back().MINumOperands) {
113 errs() << "Too few operands in record " << R->getName() <
[all...] |
| AsmWriterEmitter.cpp | 72 // Check to see if any other operands are identical in this list, and if so,
115 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
118 O << " " << FirstInst.Operands[i].getCode();
126 FirstInst.Operands[i]));
132 AWI.Operands[i]));
163 if (Inst->Operands.empty())
166 Command = " " + Inst->Operands[0].getCode() + "\n";
201 // If this instruction has no more operands, we isn't anything to merge
205 if (!FirstInst || FirstInst->Operands.size() == Op)
211 // Keep track of the maximum, number of operands or an
[all...] |
| FixedLenDecoderEmitter.cpp | 315 const std::map<unsigned, std::vector<OperandInfo> > &Operands;
339 Operands(FC.Operands), Filters(FC.Filters),
349 : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(),
362 : AllInstructions(Insts), Opcodes(IDs), Operands(Ops),
568 Owner->Operands,
601 Owner->Operands,
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| /external/llvm/include/llvm/MC/ |
| MCInst.h | 31 /// MCOperand - Instances of this class represent operands of the MCInst class.
153 SmallVector<MCOperand, 8> Operands;
163 const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
164 MCOperand &getOperand(unsigned i) { return Operands[i]; }
165 unsigned getNumOperands() const { return Operands.size(); }
168 Operands.push_back(Op);
171 void clear() { Operands.clear(); }
172 size_t size() { return Operands.size(); }
175 iterator begin() { return Operands.begin(); }
176 iterator end() { return Operands.end();
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| MCTargetAsmParser.h | 134 /// \param Operands [out] - The list of parsed operands, this returns
138 SMLoc NameLoc, OperandVector &Operands) = 0;
156 /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
163 OperandVector &Operands, MCStreamer &Out,
183 const OperandVector &Operands) = 0;
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 88 // Length is the operand length for D(L,B)-style operands, otherwise
164 // Token operands
173 // Register operands.
185 // Access register operands. Access registers aren't exposed to LLVM
191 // Immediate operands.
203 // Memory operands.
231 assert(N == 1 && "Invalid number of operands");
235 assert(N == 1 && "Invalid number of operands");
240 assert(N == 1 && "Invalid number of operands");
244 assert(N == 2 && "Invalid number of operands");
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| ScalarEvolutionExpressions.h | 140 const SCEV *const *Operands;
145 : SCEV(ID, T), Operands(O), NumOperands(N) {}
151 return Operands[i];
156 op_iterator op_begin() const { return Operands; }
157 op_iterator op_end() const { return Operands + NumOperands; }
158 op_range operands() const {
286 /// All operands of an AddRec are required to be loop invariant.
298 const SCEV *getStart() const { return Operands[0]; }
671 SmallVector<const SCEV *, 2> Operands;
673 Operands.push_back(visit(Expr->getOperand(i)))
[all...] |
| ConstantFolding.h | 11 // operands are constants, for example "sub i32 1, 0" -> "1".
36 /// Note that this fails if not all of the operands are constant. Otherwise,
51 /// specified operands. If successful, the constant result is returned, if not,
62 /// instruction (icmp/fcmp) with the specified operands. If it fails, it
63 /// returns a constant expression of the specified operands.
71 /// instruction with the specified operands and indices. The constant result is
100 Constant *ConstantFoldCall(Function *F, ArrayRef<Constant *> Operands,
|
| /external/llvm/lib/Analysis/ |
| ScalarEvolutionNormalization.cpp | 109 SmallVector<const SCEV *, 8> Operands;
111 // The addrec conceptually uses its operands at loop entry.
116 Operands.push_back(TransformSubExpr(*I, LUser, nullptr));
119 const SCEV *Result = SE.getAddRecExpr(Operands, L, SCEV::FlagAnyWrap);
191 SmallVector<const SCEV *, 8> Operands;
199 Operands.push_back(N);
204 case scAddExpr: return SE.getAddExpr(Operands);
205 case scMulExpr: return SE.getMulExpr(Operands);
206 case scSMaxExpr: return SE.getSMaxExpr(Operands);
207 case scUMaxExpr: return SE.getUMaxExpr(Operands);
[all...] |
| ConstantFolding.cpp | 258 // Otherwise, add any offset that our operands provide.
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.h | 41 SmallVectorImpl<std::unique_ptr<MCParsedAsmOperand>> &Operands,
|
| X86AsmParser.cpp | 170 assert (OperandStack.size() > 1 && "Too few operands.");
692 void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
695 OperandVector &Operands, MCStreamer &Out,
699 /// doSrcDstMatch - Returns true if operands are matching in their
705 /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
707 bool HandleAVX512Operand(OperandVector &Operands,
759 SMLoc NameLoc, OperandVector &Operands) override;
812 // Return true and let a normal complaint about bogus operands happen.
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 59 bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
61 bool parseCondCode(OperandVector &Operands, bool invertCondCode);
65 bool parseRegister(OperandVector &Operands);
67 bool parseVectorList(OperandVector &Operands);
68 bool parseOperand(OperandVector &Operands, bool isCondCode,
86 OperandVector &Operands, MCStreamer &Out,
97 OperandMatchResultTy tryParseOptionalShiftExtend(OperandVector &Operands);
98 OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
99 OperandMatchResultTy tryParseMRSSystemRegister(OperandVector &Operands);
100 OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 78 OperandVector &Operands, MCStreamer &Out,
85 bool ParseParenSuffix(StringRef Name, OperandVector &Operands);
87 bool ParseBracketSuffix(StringRef Name, OperandVector &Operands);
90 SMLoc NameLoc, OperandVector &Operands) override;
94 MipsAsmParser::OperandMatchResultTy parseMemOperand(OperandVector &Operands);
97 MatchAnyRegisterNameWithoutDollar(OperandVector &Operands,
101 MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S);
103 MipsAsmParser::OperandMatchResultTy ParseAnyRegister(OperandVector &Operands);
105 MipsAsmParser::OperandMatchResultTy ParseImm(OperandVector &Operands);
107 MipsAsmParser::OperandMatchResultTy ParseJumpTarget(OperandVector &Operands);
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 318 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
319 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
353 SMLoc NameLoc, OperandVector &Operands) override;
361 OperandVector &Operands, MCStreamer &Out,
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 50 OperandVector &Operands, MCStreamer &Out,
55 SMLoc NameLoc, OperandVector &Operands) override;
61 // Custom parse functions for Sparc specific operands.
62 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
64 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
70 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
252 assert(N == 1 && "Invalid number of operands!");
257 assert(N == 1 && "Invalid number of operands!");
273 assert(N == 2 && "Invalid number of operands!");
282 assert(N == 2 && "Invalid number of operands!");
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| ArgumentPromotion.cpp | 21 // more than three operands to the function, because passing thousands of
22 // operands for a large array or structure is unprofitable! This limit can be
268 // This load is safe if any prefix of its operands is safe to load.
385 IndicesVector Operands;
388 Operands.clear();
394 Operands.push_back(0);
411 Operands.push_back(C->getSExtValue());
430 // is safe if Operands, or a prefix of Operands, is marked as safe.
431 if (!PrefixIn(Operands, SafeToUnconditionallyLoad)
[all...] |
| /external/llvm/test/MC/X86/ |
| x86_operands.s | 30 # Indirect Memory Operands
|
| /external/llvm/lib/CodeGen/ |
| MachineInstr.cpp | 218 // Register operands don't have target flags.
547 /// implicit operands. It reserves space for the number of operands specified by
551 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0),
554 // Reserve space for the expected number of operands.
558 Operands = MF.allocateOperandArray(CapOperands);
568 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
573 Operands = MF.allocateOperandArray(CapOperands);
575 // Copy operands.
592 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands i
[all...] |
| /external/llvm/lib/IR/ |
| Metadata.cpp | 53 // Use CallbackVH to hold MDNode operands.
127 // Mark the first MDNodeOperand as being the first in the list of operands.
144 // Destroy the operands.
191 // critical code because it recursively visits all the MDNode's operands.
224 // isFunctionLocal bit because that's implied by the operands.
225 // Note that if the operands are later nulled out, the node will be
256 // Coallocate space for the node and Operands together, then placement new.
315 // isFunctionLocal bit because that's implied by the operands.
316 // Note that if the operands are later nulled out, the node will be
356 // If this node is already not being uniqued (because one of the operands
[all...] |
