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    Searched refs:PRIM_MODE_MASK (Results 1 - 14 of 14) sorted by null

  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/
intel_render.c 195 nr_rverts += length * scale_prim[prim & PRIM_MODE_MASK];
197 if (reduced_prim[prim & PRIM_MODE_MASK] != rprim) {
199 rprim = reduced_prim[prim & PRIM_MODE_MASK];
253 intel_render_tab_verts[prim & PRIM_MODE_MASK] (ctx, start,
  /external/mesa3d/src/mesa/drivers/dri/i915/
intel_render.c 195 nr_rverts += length * scale_prim[prim & PRIM_MODE_MASK];
197 if (reduced_prim[prim & PRIM_MODE_MASK] != rprim) {
199 rprim = reduced_prim[prim & PRIM_MODE_MASK];
253 intel_render_tab_verts[prim & PRIM_MODE_MASK] (ctx, start,
  /external/chromium_org/third_party/mesa/src/src/mesa/tnl/
t_vb_render.c 313 assert((prim & PRIM_MODE_MASK) <= GL_POLYGON);
317 _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
321 tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
t_context.h 177 #define PRIM_MODE_MASK 0x0f
  /external/mesa3d/src/mesa/tnl/
t_vb_render.c 313 assert((prim & PRIM_MODE_MASK) <= GL_POLYGON);
317 _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
321 tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
t_context.h 177 #define PRIM_MODE_MASK 0x0f
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
r200_tcl.c 247 tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
255 tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
272 if ((prim & PRIM_MODE_MASK) == GL_POINTS && ctx->Point.PointSprite) {
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_tcl.c 247 tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
255 tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
272 if ((prim & PRIM_MODE_MASK) == GL_POINTS && ctx->Point.PointSprite) {
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
radeon_tcl.c 236 tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
244 tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
radeon_swtcl.c 439 _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
443 tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
  /external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_tcl.c 236 tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
244 tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
radeon_swtcl.c 439 _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
443 tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
  /external/chromium_org/third_party/mesa/src/src/mesa/tnl_dd/
t_dd_dmatmp.h 1195 switch (prim & PRIM_MODE_MASK) {
1259 /* fprintf(stderr, "not ok %s\n", _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK)); */
  /external/mesa3d/src/mesa/tnl_dd/
t_dd_dmatmp.h 1195 switch (prim & PRIM_MODE_MASK) {
1259 /* fprintf(stderr, "not ok %s\n", _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK)); */

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