| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 375 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
380 SIGN_EXTEND_INREG,
398 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
129 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom)
[all...] |
| R600ISelLowering.cpp | 93 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
100 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
105 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal)
[all...] |
| AMDGPUISelLowering.cpp | 529 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
552 case ISD::SIGN_EXTEND_INREG:
554 // sign_extend_inreg is the one to check for custom lowering. The extended
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 108 //FIXME: SIGN_EXTEND_INREG is not meaningful for floating point types
110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
218 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
|
| AMDGPUISelLowering.cpp | 92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 108 //FIXME: SIGN_EXTEND_INREG is not meaningful for floating point types
110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
218 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
|
| AMDGPUISelLowering.cpp | 92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 74 case ISD::SIGN_EXTEND_INREG:
429 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
492 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
581 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
713 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
[all...] |
| SelectionDAGDumper.cpp | 223 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
|
| LegalizeVectorOps.cpp | 75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
296 case ISD::SIGN_EXTEND_INREG:
638 case ISD::SIGN_EXTEND_INREG:
[all...] |
| LegalizeVectorTypes.cpp | 62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
298 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
573 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
[all...] |
| LegalizeTypes.h | 203 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 149 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
151 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
152 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 137 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 515 IndexOpcode == ISD::SIGN_EXTEND_INREG)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 301 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
362 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
363 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 344 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
346 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
[all...] |
