| /external/llvm/lib/Target/R600/ |
| R600ExpandSpecialInstrs.cpp | 34 const R600InstrInfo *TII;
41 TII(nullptr) { }
60 int OpIdx = TII->getOperandIdx(*OldMI, Op);
63 TII->setImmOperand(NewMI, Op, Val);
68 TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
70 const R600RegisterInfo &TRI = TII->getRegisterInfo();
81 if (TII->isLDSRetInstr(MI.getOpcode())) {
82 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
85 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
88 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode()
[all...] |
| R600EmitClauseMarkers.cpp | 37 const R600InstrInfo *TII;
55 if (TII->isLDSRetInstr(MI->getOpcode()))
58 if(TII->isVector(*MI) ||
59 TII->isCubeOp(MI->getOpcode()) ||
60 TII->isReductionOp(MI->getOpcode()))
74 if (TII->isALUInstr(MI->getOpcode()))
76 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode()))
121 if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() != AMDGPU::DOT_4)
125 TII->getSrcs(MI)
[all...] |
| R600Packetizer.cpp | 61 const R600InstrInfo *TII;
76 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
88 if (TII->isPredicated(BI))
90 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
98 if (isTrans || TII->isTransOnly(BI)) {
140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
154 TII (static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo())),
155 TRI(TII->getRegisterInfo()) {
173 if (TII->isVector(*MI)
[all...] |
| R600ClauseMergePass.cpp | 47 const R600InstrInfo *TII;
76 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm();
82 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::Enabled)).getImm();
87 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
106 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
110 if (CumuledInsts >= TII->getMaxAlusPerClause()) {
118 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0);
120 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0);
122 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0);
134 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE1)
[all...] |
| SILowerControlFlow.cpp | 71 const SIInstrInfo *TII;
96 MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { }
140 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
159 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
164 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
176 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
188 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
204 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
207 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 75 const HexagonInstrInfo *TII = QTM.getInstrInfo();
96 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) {
97 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
99 TII->get(Hexagon::CONST32_Int_Real),
101 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
107 TII->get(Hexagon::STriw_indexed))
111 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
113 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
116 TII->get(Hexagon::STriw_indexed)
[all...] |
| HexagonSplitConst32AndConst64.cpp | 76 const TargetInstrInfo *TII = QTM.getInstrInfo();
93 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
95 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
106 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
108 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
119 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
121 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
132 TII->get(Hexagon::LOi), DestReg).addImm(ImmValue);
134 TII->get(Hexagon::HIi), DestReg).addImm(ImmValue);
151 TII->get(Hexagon::LOi), DestLo).addImm(LowWord)
[all...] |
| HexagonRegisterInfo.cpp | 130 const HexagonInstrInfo &TII =
145 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
146 !TII.isSpillPredRegOp(&MI)) {
153 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
175 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
177 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
179 TII.get(Hexagon::ADD_rr),
183 TII.get(Hexagon::ADD_ri),
204 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
206 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset)
[all...] |
| HexagonSplitTFRCondSets.cpp | 83 const TargetInstrInfo *TII = QTM.getInstrInfo();
115 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
119 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2),
135 TII->get(Hexagon::TFR_cPt), DestReg).
140 TII->get(Hexagon::TFRI_cNotPt), DestReg).
145 TII->get(Hexagon::TFRI_cNotPt_f), DestReg).
161 TII->get(Hexagon::TFRI_cPt), DestReg).
166 TII->get(Hexagon::TFRI_cPt_f), DestReg).
175 TII->get(Hexagon::TFR_cNotPt), DestReg).
191 TII->get(Hexagon::TFRI_cPt)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 30 const R600InstrInfo *TII;
34 TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
53 const R600RegisterInfo &TRI = TII->getRegisterInfo();
63 bool IsReduction = TII->isReductionOp(MI.getOpcode());
64 bool IsVector = TII->isVector(MI);
65 bool IsCube = TII->isCubeOp(MI.getOpcode());
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
157 TII->addFlag(NewMI, 0, Flags);
|
| SIRegisterInfo.h | 28 const TargetInstrInfo &TII;
30 SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
|
| AMDGPUConvertToISA.cpp | 49 const AMDGPUInstrInfo * TII =
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
|
| AMDGPURegisterInfo.cpp | 20 const TargetInstrInfo &tii)
23 TII(tii)
|
| R600RegisterInfo.h | 28 const TargetInstrInfo &TII;
30 R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 30 const R600InstrInfo *TII;
34 TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
53 const R600RegisterInfo &TRI = TII->getRegisterInfo();
63 bool IsReduction = TII->isReductionOp(MI.getOpcode());
64 bool IsVector = TII->isVector(MI);
65 bool IsCube = TII->isCubeOp(MI.getOpcode());
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
157 TII->addFlag(NewMI, 0, Flags);
|
| SIRegisterInfo.h | 28 const TargetInstrInfo &TII;
30 SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
|
| AMDGPUConvertToISA.cpp | 49 const AMDGPUInstrInfo * TII =
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 45 const MSP430InstrInfo &TII =
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
110 const MSP430InstrInfo &TII =
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
161 TII.get(MSP430::SUB16ri), MSP430::SPW)
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
191 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo()
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 64 auto *TII =
85 unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
95 OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
108 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
114 unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
116 BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
121 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
122 BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
131 MI->setDesc(TII->get(OpcodeForOffset));
|
| /external/llvm/lib/Target/Mips/ |
| MipsLongBranch.cpp | 172 const MipsInstrInfo *TII =
180 MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI);
219 const MipsInstrInfo *TII =
221 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
222 const MCInstrDesc &NewDesc = TII->get(NewOpc);
256 const MipsInstrInfo *TII =
293 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
314 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
317 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64StorePairSuppress.cpp | 30 const AArch64InstrInfo *TII;
82 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass();
121 TII = static_cast<const AArch64InstrInfo *>(MF->getTarget().getInstrInfo());
126 SchedModel.init(*ST.getSchedModel(), &ST, TII);
150 if (TII->getLdStBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
158 TII->suppressLdStPair(&MI);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 62 const XCoreInstrInfo &TII,
70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
93 const XCoreInstrInfo &TII,
102 TII.loadImmediate(MBB, II, ScratchOffset, Offset);
106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
129 const XCoreInstrInfo &TII,
[all...] |
| XCoreFrameToArgsOffsetElim.cpp | 45 const XCoreInstrInfo &TII =
56 MBBI = TII.loadImmediate(MBB, MBBI, Reg, StackSize);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 43 const TargetInstrInfo &TII, DebugLoc dl,
46 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
54 const Thumb1InstrInfo &TII =
75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
94 const Thumb1InstrInfo &TII =
118 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
123 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
129 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
134 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)
[all...] |
| Thumb2RegisterInfo.cpp | 43 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
49 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
|
