| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | [all...] |
| SelectionDAGNodes.h | [all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 148 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
149 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
151 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
298 return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
[all...] |
| AMDGPUISelLowering.cpp | 219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
225 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
228 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
[all...] |
| R600ISelLowering.cpp | 120 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
125 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 834 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
[all...] |
| SelectionDAGDumper.cpp | 463 case ISD::ZEXTLOAD: OS << ", zext"; break;
|
| LegalizeDAG.cpp | 532 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
534 HiExtType = ISD::ZEXTLOAD;
539 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
555 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
[all...] |
| LegalizeVectorOps.cpp | 543 case ISD::ZEXTLOAD:
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| SelectionDAG.cpp | 242 case ISD::ZEXTLOAD:
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 131 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
135 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
462 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 222 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 591 bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
621 LD->getExtensionType() == ISD::ZEXTLOAD) {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 226 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
379 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
[all...] |
| MipsSEISelLowering.cpp | 56 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 209 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 85 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 459 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 410 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
573 setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
