| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
32 addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
33 addRegisterClass(MVT::i64, &AMDGPU::VReg_64RegClass);
34 addRegisterClass(MVT::i1, &AMDGPU::SCCRegRegClass);
35 addRegisterClass(MVT::i1, &AMDGPU::VCCRegRegClass);
37 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
|
| R600ISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
32 addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
33 addRegisterClass(MVT::i64, &AMDGPU::VReg_64RegClass);
34 addRegisterClass(MVT::i1, &AMDGPU::SCCRegRegClass);
35 addRegisterClass(MVT::i1, &AMDGPU::VCCRegRegClass);
37 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
|
| R600ISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 33 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
34 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
36 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
37 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
39 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
40 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
42 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
43 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
44 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
46 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass)
[all...] |
| R600ISelLowering.cpp | 35 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
36 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
37 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
38 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
39 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
40 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 40 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
43 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
65 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
105 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
110 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
112 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
244 addRegisterClass(Ty, RC);
293 addRegisterClass(Ty, RC);
[all...] |
| Mips16ISelLowering.cpp | 125 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
657 addRegisterClass(MVT::f32, &X86::FR32RegClass);
658 addRegisterClass(MVT::f64, &X86::FR64RegClass);
691 addRegisterClass(MVT::f32, &X86::FR32RegClass);
692 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
726 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
727 addRegisterClass(MVT::f32, &X86::RFP32RegClass)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 127 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
128 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
129 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
130 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
131 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
132 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 90 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
92 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
93 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
94 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
95 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
96 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 64 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
65 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 89 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
90 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
93 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
94 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
95 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
96 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
100 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
101 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
546 addRegisterClass(VT, &AArch64::FPR64RegClass);
551 addRegisterClass(VT, &AArch64::FPR128RegClass)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass)
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 76 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 149 addRegisterClass(VT, &ARM::DPRRegClass);
154 addRegisterClass(VT, &ARM::DPairRegClass);
391 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
393 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
396 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
398 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
[all...] |
