| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| ComplexToRealFixup.S | 88 #define dW1i v17.2s
173 ld1 {dW1i},[pTwiddleTmp], #8
190 // VZIP dW1r,dW1i
192 zip1 dZip, dW1r, dW1i
193 zip2 dW1i, dW1r, dW1i
204 fmla qT0,dW1i,dT3
205 fmls qT1,dW1i,dT2
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| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S | 91 #define dW1i v7.2s
189 ld1 {dW1i},[pTwiddleTmp], #8
210 // VZIP dW1r,dW1i
212 zip1 dZip, dW1r,dW1i
213 zip2 dW1i,dW1r,dW1i
224 fmls dX1r,dW1i,dT3
225 fmla dX1i,dW1i,dT2
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| armSP_FFT_CToC_FC32_Radix4_ls_s.S | 105 #define dW1i v9.2s
141 ld2 {dW1r,dW1i},[pTwiddle] // [wi|wr]
217 fmla dZr1,dW1i,dXi1 // real part
219 fmls dZi1,dW1i,dXr1 // imag part
224 fmls dZr1,dW1i,dXi1 // real part
226 fmla dZi1,dW1i,dXr1 // imag part
230 ld2 {dW1r,dW1i},[pTwiddle],stepTwiddle // [wi|wr]
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| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_FC32_Radix4_ls_unsafe_s.S | 98 #define dW1i D9.F32
142 VLD2 {dW1r,dW1i},[pTwiddle :128] @// [wi|wr]
194 VMLA dZr1,dW1i,dXi1 @// real part
196 VMLS dZi1,dW1i,dXr1 @// imag part
201 VMLS dZr1,dW1i,dXi1 @// real part
203 VMLA dZi1,dW1i,dXr1 @// imag part
207 VLD2 {dW1r,dW1i},[pTwiddle :128],stepTwiddle @// [wi|wr]
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| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 100 #define dW1i D7.F32
207 VLD1 dW1i,[pTwiddleTmp]!
228 VZIP dW1r,dW1i
237 VMLS dX1r,dW1i,dT3
238 VMLA dX1i,dW1i,dT2
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| armSP_FFTInv_CCSToR_S32_preTwiddleRadix2_unsafe_s.S | 107 #define dW1i D7.S32
211 VLD1 dW1i,[pTwiddleTmp]!
226 VZIP dW1r,dW1i
231 VMLSL qT0,dW1i,dT3
233 VMLAL qT1,dW1i,dT2
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| armSP_FFT_CToC_SC32_Radix4_ls_unsafe_s.S | 106 #define dW1i D9.S32
150 VLD2 {dW1r,dW1i},[pTwiddle :128] @// [wi|wr]
199 VMLAL qT0,dW1i,dXi1 @// real part
201 VMLSL qT1,dW1i,dXr1 @// imag part
206 VMLSL qT0,dW1i,dXi1 @// real part
208 VMLAL qT1,dW1i,dXr1 @// imag part
212 VLD2 {dW1r,dW1i},[pTwiddle :128],stepTwiddle @// [wi|wr]
|
| omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 111 #define dW1i d17.f32
316 VLD1 dW1i,[pTwiddleTmp]!
333 VZIP dW1r,dW1i
342 VMLA qT0,dW1i,dT3
343 VMLS qT1,dW1i,dT2
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| armSP_FFT_CToC_SC16_Radix4_ls_unsafe_s.S | 111 #define dW1i D9.S16
209 VLD2 {dW1r,dW1i}, [pw1 :128]!
217 VMLAL qT0,dXi1,dW1i @// real part
219 VMLSL qT1,dXr1,dW1i @// imag part
223 VMLSL qT0,dXi1,dW1i @// real part
225 VMLAL qT1,dXr1,dW1i @// imag part
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| omxSP_FFTFwd_RToCCS_S32_Sfs_s.S | 125 #define dW1i d17.s32
457 VLD1 dW1i,[pTwiddleTmp]!
475 VZIP dW1r,dW1i
480 VMLAL qT0,dW1i,dT3
482 VMLSL qT1,dW1i,dT2
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| armSP_FFTInv_CCSToR_S16_preTwiddleRadix2_unsafe_s.S | 88 #define dW1i D7.S16
198 VLD1 dW1i,[pTwiddleTmp]!
206 VZIP dW1r,dW1i
210 VMULL qT0,dW1i,dT2
212 VMULL qT1,dW1i,dT3
329 VTRN dW1r,dW1i
333 VMLSL qT0,dW1i,dT3
335 VMLAL qT1,dW1i,dT2
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| omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 114 #define dW1i d17.s16
474 VLD1 dW1i,[pTwiddleTmp],step2r
478 VZIP dW1r, dW1i
486 VQDMULH dY0,dW1i,dT2
488 VQDMULH dY2,dW1i,dT3
581 VTRN dW1r,dW1i
585 VMLAL qT0,dW1i,dT3
587 VMLSL qT1,dW1i,dT2
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| omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 109 #define dW1i D7.F32
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| omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 126 #define dW1i D7.S32
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| omxSP_FFTInv_CCSToR_S16_Sfs_s.S | 99 #define dW1i D7.S32
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