| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| ComplexToRealFixup.S | 86 #define dW1r v16.2s
163 ld1 {dW1r},[argTwiddle], #8
190 // VZIP dW1r,dW1i
192 zip1 dZip, dW1r, dW1i
193 zip2 dW1i, dW1r, dW1i
199 fmul qT0,dW1r,dT2
200 fmul qT1,dW1r,dT3
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| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S | 89 #define dW1r v6.2s
181 ld1 {dW1r},[argTwiddle1], #8
210 // VZIP dW1r,dW1i
212 zip1 dZip, dW1r,dW1i
213 zip2 dW1i,dW1r,dW1i
219 fmul dX1r,dW1r,dT2
220 fmul dX1i,dW1r,dT3
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| armSP_FFT_CToC_FC32_Radix4_ls_s.S | 104 #define dW1r v8.2s
141 ld2 {dW1r,dW1i},[pTwiddle] // [wi|wr]
216 fmul dZr1,dW1r,dXr1
218 fmul dZi1,dW1r,dXi1
223 fmul dZr1,dW1r,dXr1
225 fmul dZi1,dW1r,dXi1
230 ld2 {dW1r,dW1i},[pTwiddle],stepTwiddle // [wi|wr]
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_FC32_Radix4_ls_unsafe_s.S | 97 #define dW1r D8.F32
142 VLD2 {dW1r,dW1i},[pTwiddle :128] @// [wi|wr]
193 VMUL dZr1,dW1r,dXr1
195 VMUL dZi1,dW1r,dXi1
200 VMUL dZr1,dW1r,dXr1
202 VMUL dZi1,dW1r,dXi1
207 VLD2 {dW1r,dW1i},[pTwiddle :128],stepTwiddle @// [wi|wr]
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| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 99 #define dW1r D6.F32
199 VLD1 dW1r,[argTwiddle1]!
228 VZIP dW1r,dW1i
232 VMUL dX1r,dW1r,dT2
233 VMUL dX1i,dW1r,dT3
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| armSP_FFTInv_CCSToR_S32_preTwiddleRadix2_unsafe_s.S | 106 #define dW1r D6.S32
203 VLD1 dW1r,[argTwiddle1]!
226 VZIP dW1r,dW1i
230 VMULL qT0,dW1r,dT2
232 VMULL qT1,dW1r,dT3
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| armSP_FFT_CToC_SC32_Radix4_ls_unsafe_s.S | 105 #define dW1r D8.S32
150 VLD2 {dW1r,dW1i},[pTwiddle :128] @// [wi|wr]
198 VMULL qT0,dW1r,dXr1
200 VMULL qT1,dW1r,dXi1
205 VMULL qT0,dW1r,dXr1
207 VMULL qT1,dW1r,dXi1
212 VLD2 {dW1r,dW1i},[pTwiddle :128],stepTwiddle @// [wi|wr]
|
| omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 110 #define dW1r d16.f32
306 VLD1 dW1r,[argTwiddle]!
333 VZIP dW1r,dW1i
337 VMUL qT0,dW1r,dT2
338 VMUL qT1,dW1r,dT3
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| armSP_FFT_CToC_SC16_Radix4_ls_unsafe_s.S | 110 #define dW1r D8.S16
209 VLD2 {dW1r,dW1i}, [pw1 :128]!
216 VMULL qT0,dXr1,dW1r
218 VMULL qT1,dXi1,dW1r
222 VMULL qT0,dXr1,dW1r
224 VMULL qT1,dXi1,dW1r
|
| omxSP_FFTFwd_RToCCS_S32_Sfs_s.S | 124 #define dW1r d16.s32
447 VLD1 dW1r,[argTwiddle]!
475 VZIP dW1r,dW1i
479 VMULL qT0,dW1r,dT2
481 VMULL qT1,dW1r,dT3
|
| armSP_FFTInv_CCSToR_S16_preTwiddleRadix2_unsafe_s.S | 87 #define dW1r D6.S16
191 VLD1 dW1r,[argTwiddle1]!
206 VZIP dW1r,dW1i
211 VMLSL qT0,dW1r,dT3
213 VMLAL qT1,dW1r,dT2
329 VTRN dW1r,dW1i
332 VMULL qT0,dW1r,dT2
334 VMULL qT1,dW1r,dT3
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| omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 113 #define dW1r d16.s16
466 VLD1 dW1r,[argTwiddle],step1r
478 VZIP dW1r, dW1i
487 VQDMULH dY1,dW1r,dT3
489 VQDMULH dY3,dW1r,dT2
581 VTRN dW1r,dW1i
584 VMULL qT0,dW1r,dT2
586 VMULL qT1,dW1r,dT3
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| omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 108 #define dW1r D6.F32
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| omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 125 #define dW1r D6.S32
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| omxSP_FFTInv_CCSToR_S16_Sfs_s.S | 98 #define dW1r D6.S32
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