| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| armSP_FFT_CToC_FC32_Radix4_s.S | 84 #define dW3 v2.2s
141 ld1 {dW3},[pTwiddle] //[wi | wr]
189 fmul dZr3,dXr3,dW3[0]
190 fmul dZi3,dXi3,dW3[0]
204 fmla dZr3,dXi3,dW3[1] // real part
205 fmls dZi3,dXr3,dW3[1] // imag part
211 fmul dZr3,dXr3,dW3[0]
212 fmul dZi3,dXi3,dW3[0]
226 fmls dZr3,dXi3,dW3[1] // real part
227 fmla dZi3,dXr3,dW3[1] // imag par
[all...] |
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_FC32_Radix4_unsafe_s.S | 81 #define dW3 D2.F32
149 VLD1 dW3,[pTwiddle] @//[wi | wr]
195 VMUL dZr3,dXr3,dW3[0]
196 VMUL dZi3,dXi3,dW3[0]
210 VMLA dZr3,dXi3,dW3[1] @// real part
211 VMLS dZi3,dXr3,dW3[1] @// imag part
217 VMUL dZr3,dXr3,dW3[0]
218 VMUL dZi3,dXi3,dW3[0]
232 VMLS dZr3,dXi3,dW3[1] @// real part
233 VMLA dZi3,dXr3,dW3[1] @// imag par
[all...] |
| armSP_FFT_CToC_SC16_Radix4_unsafe_s.S | 88 #define dW3 D2.S16
157 VLD1 dW3,[pTwiddle :64]
224 VMULL qT0,dXr3,dW3[0]
225 VMLAL qT0,dXi3,dW3[1] @// real part
226 VMULL qT1,dXi3,dW3[0]
227 VMLSL qT1,dXr3,dW3[1] @// imag part
230 VMULL qT0,dXr3,dW3[0]
231 VMLSL qT0,dXi3,dW3[1] @// real part
232 VMULL qT1,dXi3,dW3[0]
233 VMLAL qT1,dXr3,dW3[1] @// imag par
[all...] |
| armSP_FFT_CToC_SC32_Radix4_unsafe_s.S | 90 #define dW3 D2.S32
158 VLD1 dW3,[pTwiddle] @//[wi | wr]
232 VMULL qT0,dXr3,dW3[0]
233 VMLAL qT0,dXi3,dW3[1] @// real part
234 VMULL qT1,dXi3,dW3[0]
235 VMLSL qT1,dXr3,dW3[1] @// imag part
238 VMULL qT0,dXr3,dW3[0]
239 VMLSL qT0,dXi3,dW3[1] @// real part
240 VMULL qT1,dXi3,dW3[0]
241 VMLAL qT1,dXr3,dW3[1] @// imag par
[all...] |
