| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| ComplexToRealFixup.S | 73 #define dX0i v3.2s
130 mov dX0i[1],zero
134 fadd dY0r,dX0r,dX0i // F(0) = ((Z0.r+Z0.i) , 0)
136 fsub dY0i,dX0r,dX0i // F(N/2) = ((Z0.r-Z0.i) , 0)
165 ld2 {dX0r,dX0i},[pSrc],step
186 fsub dT1,dX0i,dX1i // b-d
187 fadd dT3,dX0i,dX1i // b+d
223 fmul dX0i,qT3,half[0]
225 fsub dY0r,dT0,dX0i // F(1)
|
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S | 83 #define dX0i v1.2s
183 ld2 {dX0r,dX0i},[pSrc],step
199 fadd dT3,dX0i,dX1i // b+d
201 fsub dT1,dX0i,dX1i // b-d
222 fmul dX0i,dW0r,dT3
228 fmls dX0i,dW0i,dT2
238 fadd dY0r,dT0,dX0i // F(1)
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 99 #define dX0i d3.f32
269 VLD2 {dX0r[0],dX0i[0]},[pSrc]!
273 VMOV dX0i[1],zero
277 VADD dY0r,dX0r,dX0i @// F(0) = ((Z0.r+Z0.i) , 0)
279 VSUB dY0i,dX0r,dX0i @// F(N/2) = ((Z0.r-Z0.i) , 0)
308 VLD2 {dX0r,dX0i},[pSrc],step
329 VSUB dT1,dX0i,dX1i @// b-d
330 VADD dT3,dX0i,dX1i @// b+d
361 VMUL dX0i,qT3,half[0]
363 VSUB dY0r,dT0,dX0i @// F(1
[all...] |
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 94 #define dX0i D1.F32
201 VLD2 {dX0r,dX0i},[pSrc],step
217 VADD dT3,dX0i,dX1i @// b+d
219 VSUB dT1,dX0i,dX1i @// b-d
235 VMUL dX0i,dW0r,dT3
241 VMLS dX0i,dW0i,dT2
251 VADD dY0r,dT0,dX0i @// F(1)
|
| armSP_FFTInv_CCSToR_S32_preTwiddleRadix2_unsafe_s.S | 101 #define dX0i D1.S32
205 VLD2 {dX0r,dX0i},[pSrc],step
221 VHADD dT3,dX0i,dX1i @// b+d
224 VHSUB dT1,dX0i,dX1i @// b-d
259 VRSHRN dX0i,qT3,#31
262 VHADD dY0r,dT0,dX0i @// F(1)
265 VADD dY0r,dT0,dX0i @// F(1)
|
| omxSP_FFTFwd_RToCCS_S32_Sfs_s.S | 113 #define dX0i d3.s32
412 VLD2 {dX0r[0],dX0i[0]},[pSrc]!
416 VMOV dX0i[1],zero
419 VADD dY0r,dX0r,dX0i @// F(0) = ((Z0.r+Z0.i) , 0)
421 VSUB dY0i,dX0r,dX0i @// F(N/2) = ((Z0.r-Z0.i) , 0)
449 VLD2 {dX0r,dX0i},[pSrc],step
469 VADD dT3,dX0i,dX1i @// b+d
471 VSUB dT1,dX0i,dX1i @// b-d
502 VRSHRN dX0i,qT3,#32
505 VSUB dY0r,dT0,dX0i @// F(1
[all...] |
| omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 95 #define dX0i d3.s16
426 VLD2 {dX0r[0],dX0i[0]},[pSrc]!
430 VMOV dX0i[1],zero
433 VADD dY0r,dX0r,dX0i @ F(0) = ((Z0.r+Z0.i) , 0)
435 VSUB dY0i,dX0r,dX0i @ F(N/2) = ((Z0.r-Z0.i) , 0)
459 VLD2 {dX0r,dX0i},[pSrc],step
472 VADD dT3,dX0i,dX1i @ b+d
484 VHSUB dT1,dX0i,dX1i @ (b-d)/2
500 VRHADD dX0i, d20s16, d21s16
502 VSUB dY0r,dT0,dX0i @ F(1
[all...] |
| armSP_FFTInv_CCSToR_S16_preTwiddleRadix2_unsafe_s.S | 81 #define dX0i D1.S16
185 VLD2 {dX0r,dX0i},[pSrc],step
197 VHADD dT3,dX0i,dX1i @ b+d
200 VHSUB dT1,dX0i,dX1i @ b-d
222 VRSHRN dX0i,qT3,#15
233 VHADD dY0r,dT0,dX0i @ F(1)
236 VADD dY0r,dT0,dX0i @ F(1)
306 VLD2 {dX0r[0],dX0i[0]},[pSrc]!
307 VLD2 {dX0r[1],dX0i[1]},[pSrc],step
324 VHADD dT3,dX0i,dX1i @ b+
[all...] |
| omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 103 #define dX0i D1.F32
|
| omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 120 #define dX0i D1.S32
|
| omxSP_FFTInv_CCSToR_S16_Sfs_s.S | 93 #define dX0i D1.S32
|
