| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S | 84 #define dX1r v2.2s
185 ld2 {dX1r,dX1i},[pSrc], #16
193 rev64 dX1r,dX1r
198 fsub dT2,dX0r,dX1r // a-c
200 fadd dT0,dX0r,dX1r // a+c
219 fmul dX1r,dW1r,dT2
224 fmls dX1r,dW1i,dT3
232 fsub dY1i,dX1r,dT1
|
| ComplexToRealFixup.S | 75 #define dX1r v4.2s
167 ld2 {dX1r,dX1i},[pSrc], #16
177 rev64 dX1r,dX1r
183 fsub dT2,dX0r,dX1r // a-c
185 fadd dT0,dX0r,dX1r // a+c
211 fmul dX1r,qT0,half[0]
215 fadd dY1i,dT1,dX1r
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 95 #define dX1r D2.F32
203 VLD2 {dX1r,dX1i},[pSrc]!
211 VREV64 dX1r,dX1r
216 VSUB dT2,dX0r,dX1r @// a-c
218 VADD dT0,dX0r,dX1r @// a+c
232 VMUL dX1r,dW1r,dT2
237 VMLS dX1r,dW1i,dT3
245 VSUB dY1i,dX1r,dT1
|
| armSP_FFTInv_CCSToR_S32_preTwiddleRadix2_unsafe_s.S | 102 #define dX1r D2.S32
207 VLD2 {dX1r,dX1i},[pSrc]!
215 VREV64 dX1r,dX1r
220 VHSUB dT2,dX0r,dX1r @// a-c
223 VHADD dT0,dX0r,dX1r @// a+c
241 VRSHRN dX1r,qT0,#31
246 VHSUB dY1i,dX1r,dT1
249 VSUB dY1i,dX1r,dT1
|
| omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 100 #define dX1r d4.f32
310 VLD2 {dX1r,dX1i},[pSrc]!
320 VREV64 dX1r,dX1r
326 VSUB dT2,dX0r,dX1r @// a-c
328 VADD dT0,dX0r,dX1r @// a+c
349 VMUL dX1r,qT0,half[0]
353 VADD dY1i,dT1,dX1r
|
| omxSP_FFTFwd_RToCCS_S32_Sfs_s.S | 114 #define dX1r d4.s32
451 VLD2 {dX1r,dX1i},[pSrc]!
461 VREV64 dX1r,dX1r
467 VSUB dT2,dX0r,dX1r @// a-c
470 VADD dT0,dX0r,dX1r @// a+c
490 VRSHRN dX1r,qT0,#32
494 VADD dY1i,dT1,dX1r
|
| armSP_FFTInv_CCSToR_S16_preTwiddleRadix2_unsafe_s.S | 82 #define dX1r D2.S16
186 VLD2 {dX1r,dX1i},[pSrc]!
192 VHSUB dT2,dX0r,dX1r @ a-c
199 VHADD dT0,dX0r,dX1r @ a+c
219 VRSHRN dX1r,qT0,#15
226 VHSUB dY1i,dX1r,dT1
229 VSUB dY1i,dX1r,dT1
310 VLD2 {dX1r[0],dX1i[0]},[pSrc]!
311 VLD2 {dX1r[1],dX1i[1]},[pSrc]!
319 VREV32 dX1r,dX1
[all...] |
| omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 96 #define dX1r d4.s16
460 VLD2 {dX1r,dX1i},[pSrc],stepr
468 VSUB dT2,dX0r,dX1r @ a-c
482 VHADD dT0,dX0r,dX1r @ (a+c)/2
496 VRHADD dX1r, dY0, dY1
499 VADD dY1i,dT1,dX1r
560 VLD2 {dX1r[0],dX1i[0]},[pSrc]!
561 VLD2 {dX1r[1],dX1i[1]},[pSrc]!
569 VREV32 dX1r,dX1r
[all...] |
| omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 104 #define dX1r D2.F32
|
| omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 121 #define dX1r D2.S32
|
| omxSP_FFTInv_CCSToR_S16_Sfs_s.S | 94 #define dX1r D2.S32
|
