| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| armSP_FFT_CToC_FC32_Radix4_ls_s.S | 117 #define dZr1 v26.2s
216 fmul dZr1,dW1r,dXr1
217 fmla dZr1,dW1i,dXi1 // real part
223 fmul dZr1,dW1r,dXr1
224 fmls dZr1,dW1i,dXi1 // real part
298 fadd dYr1,dZr1,dZr3
301 fsub dYr3,dZr1,dZr3
322 fsub dZr1,dYr0,dYi3
327 st2 {dZr1,dZi1},[pDst],dstStep
336 fsub dZr1,dYr0,dYi
[all...] |
| armSP_FFT_CToC_FC32_Radix4_s.S | 104 #define dZr1 v22.2s
185 fmul dZr1,dXr1,dW1[0]
192 fmla dZr1,dXi1,dW1[1] // real part
207 fmul dZr1,dXr1,dW1[0]
214 fmls dZr1,dXi1,dW1[1] // real part
258 fadd dYr1,dZr1,dZr3
259 fsub dYr3,dZr1,dZr3
281 fsub dZr1,dYr0,dYi3
285 st2 {dZr1,dZi1},[pDst],dstStep
290 fsub dZr1,dYr0,dYi
[all...] |
| armSP_FFT_CToC_FC32_Radix4_fs_s.S | 89 #define dZr1 v18.2s
195 FSUB dZr1, dYr0, dYr1
200 st2 {dZr1,dZi1},[pDst],outPointStep
229 fsub dZr1, dYr0, dYr1
234 st2 {dZr1,dZi1},[pDst],outPointStep
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_FC32_Radix4_ls_unsafe_s.S | 112 #define dZr1 D26.F32
193 VMUL dZr1,dW1r,dXr1
194 VMLA dZr1,dW1i,dXi1 @// real part
200 VMUL dZr1,dW1r,dXr1
201 VMLS dZr1,dW1i,dXi1 @// real part
283 VSUB dZr1,dYr0,dYi3
288 VST2 {dZr1,dZi1},[pDst :128],dstStep
295 VSUB dZr1,dYr0,dYi3
300 VST2 {dZr1,dZi1},[pDst :128],outPointStep
|
| armSP_FFT_CToC_FC32_Radix4_unsafe_s.S | 105 #define dZr1 D22.F32
191 VMUL dZr1,dXr1,dW1[0]
198 VMLA dZr1,dXi1,dW1[1] @// real part
213 VMUL dZr1,dXr1,dW1[0]
220 VMLS dZr1,dXi1,dW1[1] @// real part
271 VSUB dZr1,dYr0,dYi3
275 VST2 {dZr1,dZi1},[pDst :128],dstStep
280 VSUB dZr1,dYr0,dYi3
285 VST2 {dZr1,dZi1},[pDst :128],outPointStep
|
| armSP_FFT_CToC_SC16_Radix4_ls_unsafe_s.S | 148 #define dZr1 D24.S16
246 VRSHRN dZr1,qT0,#15
293 VHSUB dZr1,dYr0,dYi3 @// y1 = u0+ju3
297 VST2 {dZr1,dZi1},[pDst :128],dstStep @// dstStep = -3*outPointStep + 16
301 VHSUB dZr1,dYr0,dYi3 @// y1 = u0+ju3
307 VST2 {dZr1,dZi1},[pDst :128],outPointStep
335 VSUB dZr1,dYr0,dYi3 @// y1 = u0+ju3
339 VST2 {dZr1,dZi1},[pDst :128],dstStep @// dstStep = -3*outPointStep + 16
343 VSUB dZr1,dYr0,dYi3 @// y1 = u0+ju3
349 VST2 {dZr1,dZi1},[pDst :128],outPointSte
[all...] |
| armSP_FFT_CToC_SC32_Radix4_ls_unsafe_s.S | 120 #define dZr1 D26.S32
232 VRSHRN dZr1,qT0,#31
289 VHSUB dZr1,dYr0,dYi3
293 VST2 {dZr1,dZi1},[pDst :128],dstStep @// dstStep = -outPointStep + 16
300 VHSUB dZr1,dYr0,dYi3
305 VST2 {dZr1,dZi1},[pDst :128],outPointStep
341 VSUB dZr1,dYr0,dYi3
345 VST2 {dZr1,dZi1},[pDst :128],dstStep @// dstStep = -outPointStep + 16
352 VSUB dZr1,dYr0,dYi3
357 VST2 {dZr1,dZi1},[pDst :128],outPointSte
[all...] |
| armSP_FFT_CToC_SC32_Radix4_unsafe_s.S | 115 #define dZr1 D22.S32
226 VRSHRN dZr1,qT0,#31
277 VHSUB dZr1,dYr0,dYi3
281 VST2 {dZr1,dZi1},[pDst :128],dstStep
286 VHSUB dZr1,dYr0,dYi3
291 VST2 {dZr1,dZi1},[pDst :128],outPointStep
327 VSUB dZr1,dYr0,dYi3
331 VST2 {dZr1,dZi1},[pDst :128],dstStep
336 VSUB dZr1,dYr0,dYi3
341 VST2 {dZr1,dZi1},[pDst :128],outPointSte
[all...] |
| armSP_FFT_CToC_SC16_Radix4_fs_unsafe_s.S | 97 #define dZr1 D18.S16
191 VST2 {dZr1,dZi1},[pDst :128],outPointStep
209 VST2 {dZr1,dZi1},[pDst :128],outPointStep
245 VST2 {dZr1,dZi1},[pDst :128],outPointStep
263 VST2 {dZr1,dZi1},[pDst :128],outPointStep
|
| armSP_FFT_CToC_SC16_Radix4_unsafe_s.S | 113 #define dZr1 D22.S16
217 VRSHRN dZr1,qT0,#15
269 VST2 {dZr1,dZi1},[pDst :128],outPointStep
287 VST2 {dZr1,dZi1},[pDst :128],outPointStep
319 VST2 {dZr1,dZi1},[pDst :128],outPointStep
337 VST2 {dZr1,dZi1},[pDst :128],outPointStep
|
| armSP_FFT_CToC_SC32_Radix4_fs_unsafe_s.S | 105 #define dZr1 D18.S32
195 VST2 {dZr1,dZi1},[pDst :128],outPointStep
217 VST2 {dZr1,dZi1},[pDst :128],outPointStep
257 VST2 {dZr1,dZi1},[pDst :128],outPointStep
279 VST2 {dZr1,dZi1},[pDst :128],outPointStep
|
| armSP_FFT_CToC_FC32_Radix4_fs_unsafe_s.S | 97 #define dZr1 D18.F32
194 VST2 {dZr1,dZi1},[pDst :128],outPointStep
221 VST2 {dZr1,dZi1},[pDst :128],outPointStep
|
