/external/valgrind/main/none/tests/ppc32/ |
test_dfp3.c | 34 register double f18 __asm__ ("fr18"); 91 __asm__ __volatile__ ("drintx 1, %0, %1, 0" : "=f" (f18) : "f" (f16)); 93 __asm__ __volatile__ ("drintx 0, %0, %1, 0" : "=f" (f18) : "f" (f16)); 97 __asm__ __volatile__ ("drintx 1, %0, %1, 1" : "=f" (f18) : "f" (f16)); 99 __asm__ __volatile__ ("drintx 0, %0, %1, 1" : "=f" (f18) : "f" (f16)); 103 __asm__ __volatile__ ("drintx 1, %0, %1, 2" : "=f" (f18) : "f" (f16)); 105 __asm__ __volatile__ ("drintx 0, %0, %1, 2" : "=f" (f18) : "f" (f16)); 109 __asm__ __volatile__ ("drintx 1, %0, %1, 3" : "=f" (f18) : "f" (f16)); 111 __asm__ __volatile__ ("drintx 0, %0, %1, 3" : "=f" (f18) : "f" (f16)); 127 __asm__ __volatile__ ("drintn 1, %0, %1, 0" : "=f" (f18) : "f" (f16)) [all...] |
test_dfp2.c | 39 register double f18 __asm__ ("fr18"); 116 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0)); 120 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1)); 124 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2)); 128 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3)); 139 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0)); 143 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1)); 147 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2)); 151 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3)); 160 __asm__ __volatile__ ("dctdp %0, %1" : "=f" (f18) : "f" (f14)) [all...] |
test_dfp1.c | 33 register double f18 __asm__ ("fr18"); 85 __asm__ __volatile__ ("dadd. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); 87 __asm__ __volatile__ ("dadd %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); 93 __asm__ __volatile__ ("dsub. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); 95 __asm__ __volatile__ ("dsub %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); 101 __asm__ __volatile__ ("dmul. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); 103 __asm__ __volatile__ ("dmul %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); 109 __asm__ __volatile__ ("ddiv. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); 111 __asm__ __volatile__ ("ddiv %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)); 118 __asm__ __volatile__ ("daddq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16)) [all...] |
/external/llvm/test/MC/Mips/mips32r6/ |
invalid-mips32r2.s | 8 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 10 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 12 nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/compiler-rt/lib/builtins/ppc/ |
restFP.S | 27 lfd f18,-112(r1)
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saveFP.S | 25 stfd f18,-112(r1)
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/external/chromium_org/third_party/openssl/openssl/crypto/sha/asm/ |
sha1-sparcv9a.pl | 95 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9] 96 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9] 97 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24 99 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1 101 for %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp 156 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9] 161 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9] 166 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24 175 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&= [all...] |
/external/openssl/crypto/sha/asm/ |
sha1-sparcv9a.pl | 95 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9] 96 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9] 97 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24 99 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1 101 for %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp 156 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9] 161 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9] 166 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24 175 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&= [all...] |
/development/ndk/platforms/android-9/arch-mips/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/prebuilts/ndk/9/platforms/android-12/arch-mips/usr/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/prebuilts/ndk/9/platforms/android-13/arch-mips/usr/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/prebuilts/ndk/9/platforms/android-15/arch-mips/usr/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/prebuilts/ndk/9/platforms/android-16/arch-mips/usr/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/prebuilts/ndk/9/platforms/android-17/arch-mips/usr/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/prebuilts/ndk/9/platforms/android-19/arch-mips/usr/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
fpregdef.h | 46 #define ft5 $f18 77 #define fa6 $f18
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/external/llvm/test/MC/Mips/mips64r6/ |
invalid-mips5-wrong-error.s | 10 alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 31 cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 32 cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 38 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/clang/test/CodeGen/ |
function-attributes.c | 99 // CHECK-LABEL: define void @f18() 106 __attribute__ ((returns_twice)) void f18(void) { function
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/external/llvm/test/MC/Mips/mips1/ |
invalid-mips5-wrong-error.s | 11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 28 cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/llvm/test/MC/Mips/mips2/ |
invalid-mips5-wrong-error.s | 11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 28 cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/llvm/test/MC/Mips/mips3/ |
invalid-mips5-wrong-error.s | 11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 28 cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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