/external/valgrind/main/none/tests/mips32/ |
MoveIns.stdout.exp | 113 MOVF 114 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 115 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0 116 movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1 117 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 118 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 119 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0 120 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1 121 movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0 122 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: [all...] |
/external/llvm/test/MC/Mips/ |
micromips-movcond-instructions.s | 15 # CHECK-EL: movf $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x01] 22 # CHECK-EB: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b] 26 movf $9, $6, $fcc0
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mips-fpu-instructions.s | 163 # CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00] 166 # CHECK: movf.d $f4, $f6, $fcc2 # encoding: [0x11,0x31,0x28,0x46] 167 # CHECK: movf.s $f4, $f6, $fcc5 # encoding: [0x11,0x31,0x14,0x46] 198 movf $2, $1, $fcc0 201 movf.d $f4, $f6, $fcc2 202 movf.s $f4, $f6, $fcc5
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micromips-fpu-instructions.s | 62 # CHECK-EL: movf.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x00] 63 # CHECK-EL: movf.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x02] 125 # CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20] 126 # CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20] 184 movf.s $f4, $f6, $fcc0 185 movf.d $f4, $f6, $fcc0
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/external/llvm/test/MC/Mips/mips3/ |
invalid-mips4.s | 12 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 13 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 14 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 15 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 16 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 17 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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invalid-mips5.s | 13 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 14 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 15 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 16 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 17 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 18 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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invalid-mips5-wrong-error.s | 33 movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/llvm/test/MC/Mips/mips2/ |
invalid-mips32.s | 22 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 23 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 24 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 25 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 26 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 27 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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invalid-mips32r2.s | 29 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 30 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 31 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 32 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 33 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 34 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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invalid-mips4.s | 51 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 52 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 53 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 54 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 55 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 56 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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invalid-mips5.s | 50 movf $gp,$a0,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 51 movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 52 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 53 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 54 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 55 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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invalid-mips5-wrong-error.s | 33 movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/llvm/test/MC/Mips/mips32r6/ |
invalid-mips32.s | 12 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 13 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 14 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips64r6/ |
invalid-mips64.s | 26 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 27 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 28 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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invalid-mips5-wrong-error.s | 35 movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/llvm/test/MC/Mips/mips1/ |
invalid-mips4.s | 55 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 56 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 57 movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 58 movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 59 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 60 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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invalid-mips5.s | 54 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 55 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 56 movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 57 movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 58 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 59 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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invalid-mips5-wrong-error.s | 33 movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/chromium_org/v8/test/cctest/ |
test-disasm-mips.cc | 398 COMPARE(movf(a0, a1, 0), 399 "00a02001 movf a0, a1, 0"); 400 COMPARE(movf(s0, s1, 4), 401 "02308001 movf s0, s1, 4"); 402 COMPARE(movf(t2, t3, 5), 403 "01745001 movf t2, t3, 5"); 404 COMPARE(movf(v0, v1, 6), 405 "00781001 movf v0, v1, 6");
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/external/llvm/test/MC/Mips/mips32/ |
valid.s | 79 movf $gp,$8,$fcc7 80 movf.d $f6,$f11,$fcc5 81 movf.s $f23,$f5,$fcc6
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/external/llvm/test/MC/Mips/mips32r2/ |
valid.s | 92 movf $gp,$8,$fcc7 93 movf.d $f6,$f11,$fcc5 94 movf.s $f23,$f5,$fcc6
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/external/llvm/test/MC/Mips/mips4/ |
valid.s | 126 movf $gp,$8,$fcc7 127 movf.d $f6,$f11,$fcc5 128 movf.s $f23,$f5,$fcc6
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invalid-mips5-wrong-error.s | 33 movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/llvm/test/MC/Mips/mips5/ |
valid.s | 127 movf $gp,$8,$fcc7 128 movf.d $f6,$f11,$fcc5 129 movf.s $f23,$f5,$fcc6
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/external/llvm/test/MC/Mips/mips64/ |
valid.s | 137 movf $gp,$8,$fcc7 138 movf.d $f6,$f11,$fcc5 139 movf.s $f23,$f5,$fcc6
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