| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 99 v16f32 = 49, // 16 x f32 enumerator in enum:llvm::MVT::SimpleValueType
225 return (SimpleTy == MVT::v8f64 || SimpleTy == MVT::v16f32 ||
304 case v16f32: return f32;
326 case v16f32: return 16;
426 case v16f32:
558 if (NumElements == 16) return MVT::v16f32;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 258 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
259 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
260 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
261 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
285 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
286 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 167 case MVT::v16f32: return "v16f32";
235 case MVT::v16f32: return VectorType::get(Type::getFloatTy(Context), 16);
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 108 case MVT::v16f32: return "MVT::v16f32";
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 53 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
75 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
179 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
[all...] |
| AMDGPUISelLowering.cpp | 151 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
152 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
197 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
198 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
