| /prebuilts/gcc/darwin-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/ |
| msa.h | 49 typedef double v2f64 __attribute__ ((vector_size(16), aligned(16))); typedef
[all...] |
| /prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/ |
| msa.h | 49 typedef double v2f64 __attribute__ ((vector_size(16), aligned(16))); typedef
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 310 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
313 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
329 // Complex: to v2f64
330 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
331 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
332 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
333 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
334 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
335 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
341 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }
[all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
| AArch64ISelLowering.cpp | 111 addQRTypeForNEON(MVT::v2f64);
464 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
484 } else if (VT == MVT::v2f64 || VT == MVT::v4f32) {
493 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 37 // For the 2nd half of a v2f64, do not fail.
64 if (LocVT == MVT::v2f64 &&
86 // For the 2nd half of a v2f64, do not just fail.
118 if (LocVT == MVT::v2f64 &&
150 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
208 case MVT::v2f64:
240 if (LocVT.SimpleTy == MVT::v2f64 || LocVT.SimpleTy == MVT::i32) {
|
| ARMTargetTransformInfo.cpp | 191 { ISD::FP_ROUND, MVT::v2f64, 2 },
271 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
272 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
274 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
275 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
276 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
277 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
278 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
279 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
281 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }
[all...] |
| ARMISelLowering.cpp | 155 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
432 addQRTypeForNEON(MVT::v2f64);
438 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
442 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
443 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
444 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
447 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
448 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
452 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
455 setOperationAction(ISD::SETCC, MVT::v2f64, Expand)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 101 v2f64 = 51, // 2 x f64 enumerator in enum:llvm::MVT::SimpleValueType
213 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
306 case v2f64:
350 case v2f64: return 2;
415 case v2f64: return 128;
562 if (NumElements == 2) return MVT::v2f64;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 65 (int)MVT::v2f64,
93 (int)MVT::v2f64,
188 // we support loading/storing v2f64 but not operations on the type
189 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
190 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
191 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
192 setOperationAction(ISD::FP_ROUND_INREG, MVT::v2f64, Expand);
193 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
197 setOperationAction(ISD::TRUNCATE, MVT::v2f64, Expand);
198 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 65 (int)MVT::v2f64,
93 (int)MVT::v2f64,
188 // we support loading/storing v2f64 but not operations on the type
189 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
190 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
191 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
192 setOperationAction(ISD::FP_ROUND_INREG, MVT::v2f64, Expand);
193 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
197 setOperationAction(ISD::TRUNCATE, MVT::v2f64, Expand);
198 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 458 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
481 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd
500 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd
534 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
535 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
536 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
537 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
538 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
539 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
540 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| X86FastISel.cpp | 460 case MVT::v2f64:
[all...] |
| /external/clang/test/CodeGen/ |
| builtins-mips-msa.c | 15 typedef double v2f64 __attribute__ ((vector_size(16))); typedef
50 v2f64 v2f64_a = (v2f64) {0.5, 1};
51 v2f64 v2f64_b = (v2f64) {1.5, 2};
52 v2f64 v2f64_r;
[all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 169 case MVT::v2f64: return "v2f64";
237 case MVT::v2f64: return VectorType::get(Type::getDoubleTy(Context), 2);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 310 DecodeSHUFPMask(MVT::v2f64,
359 DecodeUNPCKLMask(MVT::v2f64, ShuffleMask);
395 DecodeUNPCKHMask(MVT::v2f64, ShuffleMask);
450 DecodePSHUFMask(MVT::v2f64,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 394 if (LT.second == MVT::v2f64 || LT.second == MVT::v2i64)
|
| PPCISelDAGToDAG.cpp | 669 else if (VecVT == MVT::v2f64)
684 else if (VecVT == MVT::v2f64)
701 else if (VecVT == MVT::v2f64)
709 else if (VecVT == MVT::v2f64)
715 else if (VecVT == MVT::v2f64)
737 case MVT::v2f64:
[all...] |
| PPCISelLowering.cpp | 538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 217 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
258 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
|
| MipsSEISelLowering.cpp | 95 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 110 case MVT::v2f64: return "MVT::v2f64";
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 157 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
158 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
203 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
204 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 66 case MVT::v2f64:
[all...] |
