| /prebuilts/gcc/darwin-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/ |
| msa.h | 47 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
[all...] |
| /prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/ |
| msa.h | 47 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 424 // 64-bit packed float vectors (v2f32) are widened to type v4f32.
461 // nodes. A v4i32/v4f32 BLENDI generates a single 'blendps'/'blendpd'.
463 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1},
486 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
503 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, // shufps + pshufd
543 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
544 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
545 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
546 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
547 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 309 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
312 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
323 // Complex: to v4f32
324 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
325 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
326 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
327 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
340 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
343 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
354 // Complex, from v4f32: legal type is v4i16, 1 narrowing => ~
[all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 193 { ISD::FP_EXTEND, MVT::v4f32, 4 }
239 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
240 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
248 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
249 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
250 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
251 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
252 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
253 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
263 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }
[all...] |
| ARMISelLowering.cpp | 431 addQRTypeForNEON(MVT::v4f32);
440 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
441 // supported for v4f32.
477 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
478 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
479 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
480 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
481 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
482 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
483 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand)
[all...] |
| /external/clang/test/CodeGen/ |
| x86_64-arguments.c | 155 typedef float v4f32 __attribute__((__vector_size__(16))); typedef
156 v4f32 f25(v4f32 X) {
179 v4f32 v;
|
| builtins-mips-msa.c | 14 typedef float v4f32 __attribute__ ((vector_size(16))); typedef
47 v4f32 v4f32_a = (v4f32) {0.5, 1, 2, 3};
48 v4f32 v4f32_b = (v4f32) {1.5, 2, 3, 4};
49 v4f32 v4f32_r;
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 97 v4f32 = 47, // 4 x f32 enumerator in enum:llvm::MVT::SimpleValueType
213 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
302 case v4f32:
341 case v4f32:
414 case v4f32:
556 if (NumElements == 4) return MVT::v4f32;
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 165 case MVT::v4f32: return "v4f32";
233 case MVT::v4f32: return VectorType::get(Type::getFloatTy(Context), 4);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600GenRegisterInfo.pl | 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
|
| AMDILISelLowering.cpp | 61 (int)MVT::v4f32,
89 (int)MVT::v4f32,
505 FLTTY = MVT::v4f32;
|
| R600ISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
|
| SIISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 335 DecodeSHUFPMask(MVT::v4f32,
377 DecodeUNPCKLMask(MVT::v4f32, ShuffleMask);
413 DecodeUNPCKHMask(MVT::v4f32, ShuffleMask);
430 DecodePSHUFMask(MVT::v4f32,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600GenRegisterInfo.pl | 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
|
| AMDILISelLowering.cpp | 61 (int)MVT::v4f32,
89 (int)MVT::v4f32,
505 FLTTY = MVT::v4f32;
|
| R600ISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 652 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
666 // v4f32 != v4f32 could be translate to unordered not equal
667 else if (VecVT == MVT::v4f32)
682 else if (VecVT == MVT::v4f32)
699 if (VecVT == MVT::v4f32)
707 if (VecVT == MVT::v4f32)
713 if (VecVT == MVT::v4f32)
726 // types (v16i8, v8i16, v4i32, and v4f32).
735 case MVT::v4f32
[all...] |
| PPCISelLowering.cpp | 496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 215 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
256 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 145 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
146 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
191 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
192 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
207 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
330 MVT::v2f32, MVT::v4f32
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 106 case MVT::v4f32: return "MVT::v4f32";
|
