| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 206 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
216 { ISD::SHL, MVT::v4i64, 1 },
217 { ISD::SRL, MVT::v4i64, 1 },
227 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
233 { ISD::SDIV, MVT::v4i64, 4*20 },
237 { ISD::UDIV, MVT::v4i64, 4*20 },
318 { ISD::SHL, MVT::v4i64, 4*10 }, // Scalarized.
360 { ISD::SUB, MVT::v4i64, 4 },
361 { ISD::ADD, MVT::v4i64, 4 },
362 // A v4i64 multiply is custom lowered as two split v2i64 vectors that the
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 85 v4i64 = 39, // 4 x i64 enumerator in enum:llvm::MVT::SimpleValueType
220 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64);
294 case v4i64:
339 case v4i64:
419 case v4i64:
544 if (NumElements == 4) return MVT::v4i64;
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 157 case MVT::v4i64: return "v4i64";
225 case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4);
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 219 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
223 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
224 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
407 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
|
| ARMISelDAGToDAG.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 227 DecodeUNPCKHMask(MVT::v4i64, ShuffleMask);
300 DecodeUNPCKLMask(MVT::v4i64, ShuffleMask);
471 // For instruction comments purpose, assume the 256-bit vector is v4i64.
473 DecodeVPERM2X128Mask(MVT::v4i64,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 454 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost },
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 98 case MVT::v4i64: return "MVT::v4i64";
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 179 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
[all...] |
