| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/machine/ |
| regnum.h | 68 #define SR 32
69 #define PS SR /* alias for SR */
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| CheckerManager.cpp | 422 SymbolReaper &SR;
430 CheckDeadSymbolsContext(const CheckersTy &checkers, SymbolReaper &sr,
433 : Checkers(checkers), SR(sr), S(s), Eng(eng), ProgarmPointKind(K) { }
444 checkFn(SR, C);
|
| MemRegion.cpp | 154 if (const SubRegion* sr = dyn_cast<SubRegion>(r))
155 r = sr->getSuperRegion();
166 if (const SubRegion *sr = dyn_cast<SubRegion>(superRegion)) {
167 r = sr;
[all...] |
| RegionStore.cpp | 422 const SubRegion *SR = cast<SubRegion>(R);
423 assert(SR->getAsOffset().getOffset() ==
424 SR->getSuperRegion()->getAsOffset().getOffset() &&
426 B = removeSubRegionBindings(B, SR);
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| IntegerDivision.cpp | 244 // ; %sr = sub nsw i32 %tmp0, %tmp1
245 // ; %ret0_4 = icmp ugt i32 %sr, 31
247 // ; %retDividend = icmp eq i32 %sr, 31
257 Value *SR = Builder.CreateSub(Tmp0, Tmp1);
258 Value *Ret0_4 = Builder.CreateICmpUGT(SR, MSB);
260 Value *RetDividend = Builder.CreateICmpEQ(SR, MSB);
266 // ; %sr_1 = add i32 %sr, 1
267 // ; %tmp2 = sub i32 31, %sr
272 Value *SR_1 = Builder.CreateAdd(SR, One);
273 Value *Tmp2 = Builder.CreateSub(MSB, SR);
[all...] |
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 737 SetVector<const CodeGenRegister*> SR;
738 Reg->addSubRegsPreOrder(SR, RegBank);
739 diffEncode(SubRegLists[i], Reg->EnumValue, SR.begin(), SR.end());
744 for (unsigned j = 0, je = SR.size(); j != je; ++j)
745 SRIs.push_back(Reg->getSubRegIndex(SR[j]));
[all...] |
| CodeGenRegisters.cpp | 215 CodeGenRegister *SR = I->second;
217 mergeRegUnits(RegUnits, SR->RegUnits);
231 CodeGenRegister *SR = ExplicitSubRegs[i];
233 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
238 SubReg2Idx.insert(std::make_pair(SR, Idx));
247 CodeGenRegister *SR = ExplicitSubRegs[i];
248 const SubRegMap &Map = SR->computeSubRegs(RegBank);
265 CodeGenRegister *SR = SubRegs[Idx];
266 const SubRegMap &Map = SR->computeSubRegs(RegBank);
269 // They may not all be supported by SR
[all...] |
| /external/clang/test/SemaCXX/ |
| overload-call.cpp | 296 struct SR {
297 SR(const string&);
300 void f(SR) { }
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | [all...] |
| /libcore/luni/src/test/java/libcore/java/util/ |
| EnumSetTest.java | 103 FE, CO, NI, CU, ZN, GA, GE, AS, SE, BR, KR, RB, SR, Y, ZR, NB, MO, TC, RU, RH, PD, AG, CD,
|
| /external/chromium_org/third_party/webrtc/modules/rtp_rtcp/source/ |
| rtcp_utility.h | 220 RTCPPacketSR SR;
371 State_ReportBlockItem, // SR/RR report block
|
| /external/clang/lib/AST/ |
| MicrosoftMangle.cpp | 421 SourceRange SR = VD->getSourceRange();
425 mangleType(Ty, SR, QMM_Drop);
443 mangleType(Ty, SR, QMM_Drop);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 758 unsigned R = 0, SR = 0;
761 SR = Start->getSubReg();
764 SR = End->getSubReg();
769 if (!SR && RC == &Hexagon::DoubleRegsRegClass)
[all...] |
| /external/chromium_org/third_party/libaddressinput/src/java/src/com/android/i18n/addressinput/ |
| RegionDataConstants.java | 1052 SR(new String[]{
[all...] |
| /external/clang/lib/Sema/ |
| SemaStmt.cpp | [all...] |
| SemaTemplate.cpp | [all...] |
| SemaChecking.cpp | [all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
| /external/clang/tools/c-index-test/ |
| c-index-test.c | [all...] |
| /external/clang/include/clang/Sema/ |
| DeclSpec.h | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/qemu/disas/ |
| ppc.c | 794 /* The SR field in an X form instruction. */
795 #define SR SPRG + 1
799 #define STRM SR + 1
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /prebuilts/misc/common/groovy/ |
| groovy-all-1.7.0.jar | |
| /prebuilts/tools/common/m2/repository/com/cenqua/clover/clover/3.1.12/ |
| clover-3.1.12.jar | |
