| /external/llvm/include/llvm/CodeGen/ |
| StackProtector.h | 51 const TargetMachine *TM;
109 : FunctionPass(ID), TM(nullptr), TLI(nullptr), SSPBufferSize(0) {
112 StackProtector(const TargetMachine *TM)
113 : FunctionPass(ID), TM(TM), TLI(nullptr), Trip(TM->getTargetTriple()),
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| DFAPacketizer.h | 94 const TargetMachine &TM;
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| FastISel.h | 57 const TargetMachine &TM;
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| MachineConstantPool.h | 135 const TargetMachine &TM; ///< The target machine.
144 explicit MachineConstantPool(const TargetMachine &TM)
145 : TM(TM), PoolAlignment(1) {}
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| FunctionLoweringInfo.h | 53 const TargetMachine &TM;
124 explicit FunctionLoweringInfo(const TargetMachine &TM) : TM(TM) {}
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| /external/llvm/lib/Target/Mips/ |
| MipsTargetMachine.cpp | 85 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
86 : TargetPassConfig(TM, PM) {
168 MipsTargetMachine &TM = getMipsTargetMachine();
169 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
170 addPass(createMipsDelaySlotFillerPass(TM));
173 addPass(createMipsLongBranchPass(TM));
176 addPass(createMipsConstantIslandPass(TM));
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| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 36 SparcTargetMachine &TM;
38 explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
39 : SelectionDAGISel(tm),
40 Subtarget(tm.getSubtarget<SparcSubtarget>()),
41 TM(tm) {
69 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
219 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
220 return new SparcDAGToDAGISel(TM);
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| DelaySlotFiller.cpp | 44 TargetMachine &TM;
48 Filler(TargetMachine &tm)
49 : MachineFunctionPass(ID), TM(tm),
50 Subtarget(&TM.getSubtarget<SparcSubtarget>()) {
102 FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
103 return new Filler(tm);
113 const TargetInstrInfo *TII = TM.getInstrInfo();
190 slot->setDesc(TM.getInstrInfo()->get(SP::RET));
332 for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 36 TargetMachine &TM;
42 SIAssignInterpRegsPass(TargetMachine &tm) :
43 MachineFunctionPass(ID), TM(tm) { }
63 FunctionPass *llvm::createSIAssignInterpRegsPass(TargetMachine &tm) {
64 return new SIAssignInterpRegsPass(tm);
126 const TargetInstrInfo * TII = TM.getInstrInfo();
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| /external/chromium_org/third_party/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
| SkPdfFieldDictionary_autogen.cpp | 71 SkString SkPdfFieldDictionary::TM(SkPdfNativeDoc* doc) {
72 SkPdfNativeObject* ret = get("TM", "");
80 return get("TM", "") != NULL;
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| /external/llvm/lib/ExecutionEngine/JIT/ |
| JIT.h | 58 TargetMachine &TM; // The current target we are compiling to
81 JIT(Module *M, TargetMachine &tm, TargetJITInfo &tji,
189 TargetMachine *TM);
197 TargetMachine *getTargetMachine() override { return &TM; }
215 TargetMachine &tm);
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| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 105 const ARMTargetMachine *TM =
107 if (TM->getRelocationModel() != Reloc::PIC_)
112 unsigned PCAdj = TM->getSubtarget<ARMSubtarget>().isThumb() ? 4 : 8;
116 unsigned Align = TM->getDataLayout()
125 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ?
127 const TargetInstrInfo &TII = *TM->getInstrInfo();
137 Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? ARM::tPICADD
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.h | 49 const TargetMachine &TM;
56 Hexagon_CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM,
64 const TargetMachine &getTarget() const { return TM; }
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPrologEpilogPass.cpp | 50 const TargetMachine &TM = MF.getTarget();
51 const TargetFrameLowering &TFI = *TM.getFrameLowering();
52 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
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| /external/llvm/lib/Target/PowerPC/ |
| PPCCodeEmitter.cpp | 31 TargetMachine &TM;
47 PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
48 : MachineFunctionPass(ID), TM(tm), MCE(mce) {}
94 FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
96 return new PPCCodeEmitter(TM, JCE);
136 assert(TM.getRelocationModel() == Reloc::PIC_);
151 return 0x80 >> TM.getRegisterInfo()->getEncodingValue(MO.getReg());
162 if (TM.getRelocationModel() == Reloc::PIC_) {
285 return TM.getRegisterInfo()->getEncodingValue(MO.getReg())
[all...] |
| PPCMCInstLower.cpp | 38 const TargetMachine &TM = AP.TM;
40 const DataLayout *DL = TM.getDataLayout();
60 TM.getNameWithPrefix(Name, GV, *Mang);
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| /external/llvm/lib/Target/X86/ |
| X86PadShortFunction.cpp | 54 , Threshold(4), TM(nullptr), TII(nullptr) {}
82 const TargetMachine *TM;
104 TM = &MF.getTarget();
105 if (!TM->getSubtarget<X86Subtarget>().padShortFunctions())
108 TII = TM->getInstrInfo();
198 CyclesToEnd += TII->getInstrLatency(TM->getInstrItineraryData(), MI);
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| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 97 explicit XCoreTargetLowering(const TargetMachine &TM);
126 const TargetMachine &TM;
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| /external/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
| SkPdfFieldDictionary_autogen.cpp | 71 SkString SkPdfFieldDictionary::TM(SkPdfNativeDoc* doc) {
72 SkPdfNativeObject* ret = get("TM", "");
80 return get("TM", "") != NULL;
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| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
| lp_bld_debug.cpp | 278 TargetMachine *TM = T->createTargetMachine(Triple, sys::getHostCPUName(), "", options);
280 TargetMachine *TM = T->createTargetMachine(Triple, sys::getHostCPUName(), "");
282 TargetMachine *TM = T->createTargetMachine(Triple, "");
285 const TargetInstrInfo *TII = TM->getInstrInfo();
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| /external/llvm/lib/CodeGen/ |
| AtomicExpandLoadLinkedPass.cpp | 32 const TargetMachine *TM;
35 explicit AtomicExpandLoadLinked(const TargetMachine *TM = nullptr)
36 : FunctionPass(ID), TM(TM) {
59 FunctionPass *llvm::createAtomicExpandLoadLinkedPass(const TargetMachine *TM) {
60 return new AtomicExpandLoadLinked(TM);
64 if (!TM || !TM->getSubtargetImpl()->enableAtomicExpandLoadLinked())
81 if (!TM->getTargetLowering()->shouldExpandAtomicInIR(Inst))
103 TM->getTargetLowering()->getInsertFencesForAtomic() ? Monotoni
[all...] |
| DwarfEHPrepare.cpp | 36 const TargetMachine *TM;
46 DwarfEHPrepare(const TargetMachine *TM)
47 : FunctionPass(ID), TM(TM), RewindFunction(nullptr) {
63 FunctionPass *llvm::createDwarfEHPass(const TargetMachine *TM) {
64 return new DwarfEHPrepare(TM);
121 const TargetLowering *TLI = TM->getTargetLowering();
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| RegisterScavenging.cpp | 73 const TargetMachine &TM = MF.getTarget();
74 TII = TM.getInstrInfo();
75 TRI = TM.getRegisterInfo();
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| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 372 const TargetMachine &TM = mf.getTarget();
374 TII = static_cast<const AArch64InstrInfo *>(TM.getInstrInfo());
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| AArch64TargetTransformInfo.cpp | 39 const AArch64TargetMachine *TM;
48 AArch64TTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) {
52 AArch64TTI(const AArch64TargetMachine *TM)
53 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
54 TLI(TM->getTargetLowering()) {
137 llvm::createAArch64TargetTransformInfoPass(const AArch64TargetMachine *TM) {
138 return new AArch64TTI(TM);
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