| /external/llvm/test/Transforms/LoopVectorize/ |
| same-base-access.ll | 46 %20 = fadd double %14, %19
|
| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| ordering.ll | 16 %add = fadd double %mul4, %mul8
|
| /external/llvm/test/Transforms/ScalarRepl/ |
| copy-aggregate.ll | 33 %c = fadd float %a, %b
|
| /external/llvm/utils/vim/ |
| llvm.vim | 27 syn keyword llvmStatement extractvalue fadd fast fcmp fdiv fence fmul fpext
|
| /external/valgrind/main/none/tests/ppc32/ |
| round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD,
43 "fadd", "fsub", "fmul", "fdiv", "fmadd", "fmsub", "fnmadd",
465 BINOP("fadd");
913 case FADD:
1080 case FADD:
1081 BINOP("fadd");
1181 for (op = FADD; op <= FSQRT; op++) {
|
| /external/valgrind/main/none/tests/ppc64/ |
| round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD,
43 "fadd", "fsub", "fmul", "fdiv", "fmadd", "fmsub", "fnmadd",
465 BINOP("fadd");
913 case FADD:
1080 case FADD:
1081 BINOP("fadd");
1181 for (op = FADD; op <= FSQRT; op++) {
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrFP.td | 317 def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32, FP32>;
318 def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64, FP64>;
319 def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>;
321 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>;
322 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>;
|
| /external/llvm/test/CodeGen/PowerPC/ |
| 2011-12-05-NoSpillDupCR.ll | 53 %add8.us = fadd float %3, %2
88 %add8.us.1 = fadd float %6, %5
110 %add8.us.2 = fadd float %9, %8
132 %add8.us.3 = fadd float %12, %11
154 %add8.us.4 = fadd float %15, %14
|
| /external/llvm/test/CodeGen/X86/ |
| sse41.ll | 121 %t = fadd float %s, 1.0
235 %add.r = fadd float %tmp7, %tmp3
236 %add.i = fadd float %tmp5, %tmp1
690 %11 = fadd <4 x float> %7, %8
691 %12 = fadd <4 x float> %9, %10
692 %13 = fadd <4 x float> %11, %12
|
| sse2.ll | 154 %tmp4 = fadd <4 x float> %tmp2, %tmp3 ; <<4 x float>> [#uses=1]
176 %tmp9 = fadd <4 x float> %tmp5, %tmp ; <<4 x float>> [#uses=1]
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| SLPVectorizer.cpp | 156 case Instruction::FAdd:
159 return Instruction::FAdd;
173 if (Op == Instruction::FAdd || Op == Instruction::FSub ||
180 /// alternate fadd,fsub / fsub,fadd/add,sub/sub,add sequence.
181 /// (i.e. e.g. opcodes of fadd,fsub,fadd,fsub...)
946 case Instruction::FAdd:
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 305 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
307 /// expanded to fmul + fadd.
|
| /external/llvm/test/CodeGen/ARM/ |
| vadd.ll | 44 %tmp3 = fadd <2 x float> %tmp1, %tmp2
89 %tmp3 = fadd <4 x float> %tmp1, %tmp2
|
| vmla.ll | 43 %tmp5 = fadd <2 x float> %tmp1, %tmp4
87 %tmp5 = fadd <4 x float> %tmp1, %tmp4
|
| interrupt-attr.ll | 131 %sum = fadd double %lhs, %rhs
|
| vuzp.ll | 73 %tmp5 = fadd <4 x float> %tmp3, %tmp4
|
| vzip.ll | 73 %tmp5 = fadd <4 x float> %tmp3, %tmp4
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-scalar-fp.txt | 16 # CHECK: fadd s1, s2, s3
17 # CHECK: fadd d1, d2, d3
|
| /external/llvm/test/Transforms/InstCombine/ |
| shufflemask-undef.ll | 80 fadd <4 x float> zeroinitializer, %7 ; <<4 x float>>:8 [#uses=1]
86 fadd <4 x float> %tmp4117.i, zeroinitializer ; <<4 x float>>:10 [#uses=1]
|
| /bionic/libc/kernel/uapi/linux/ |
| rds.h | 184 } fadd; member in union:rds_atomic_args::__anon770
|
| /development/ndk/platforms/android-L/include/linux/ |
| rds.h | 184 } fadd; member in union:rds_atomic_args::__anon2344
|
| /external/clang/test/CodeGenCXX/ |
| mangle-lambdas.cpp | 88 // CHECK-NEXT: fadd double
|
| /external/llvm/test/CodeGen/SPARC/ |
| float.ll | 77 %3 = fadd double %2, %2
|
| /external/llvm/test/MC/AArch64/ |
| arm64-fp-encoding.s | 14 fadd s1, s2, s3
15 fadd d1, d2, d3
17 ; CHECK: fadd s1, s2, s3 ; encoding: [0x41,0x28,0x23,0x1e]
18 ; CHECK: fadd d1, d2, d3 ; encoding: [0x41,0x28,0x63,0x1e]
|
