| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCExpr.h | 11 // ":lo12:" or ":gottprel_g1:".
54 // is unfortunately sometimes omitted from the assembly syntax. E.g. :lo12:
62 // since a user would write ":lo12:").
145 /// (e.g. ":got:", ":lo12:").
|
| AArch64MCExpr.cpp | 11 // accepted by the AArch64 architecture (e.g. ":lo12:", ":gottprel_g1:", ...).
36 case VK_LO12: return ":lo12:";
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-2012-05-07-MemcpyAlignBug.ll | 10 ; CHECK: add x[[ADDR:[0-9]+]], x[[PAGE]], {{l_b@PAGEOFF|:lo12:.Lb}}
|
| arm64-jumptable.ll | 35 ; CHECK-LINUX: add {{x[0-9]+}}, {{x[0-9]+}}, :lo12:.LJTI0_0
|
| blockaddress.ll | 12 ; CHECK: add [[DEST:x[0-9]+]], [[DEST_HI]], {{#?}}:lo12:[[DEST_LBL]]
|
| arm64-ldxr-stxr.ll | 40 ; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
54 ; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
68 ; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
80 ; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
177 ; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
191 ; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
205 ; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
217 ; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
|
| jump-table.ll | 15 ; CHECK: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0
27 ; CHECK-PIC: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0
|
| literal_pools_float.ll | 15 ; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
32 ; CHECK: ldr [[LIT129:d[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
|
| arm64-blockaddress.ll | 15 ; CHECK-LINUX: add {{x[0-9]+}}, [[REG]], :lo12:.Ltmp1
|
| arm64-hello.ll | 22 ; CHECK-LINUX: add x0, x0, :lo12:.L.str
|
| arm64-extern-weak.ll | 45 ; CHECK: add x0, [[BASE]], :lo12:defined_weak_var
|
| arm64-neon-simd-ldst-one.ll | 47 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
56 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
65 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
74 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
83 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
92 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
101 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
110 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
119 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
|
| extern-weak.ll | 50 ; CHECK: add x0, [[BASE]], :lo12:defined_weak_var
|
| sibling-call.ll | 94 ; CHECK: ldr [[FPTR:x[1-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:func]
|
| ldst-unscaledimm.ll | 163 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
172 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
|
| neon-mov.ll | 255 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
|
| /bionic/libc/arch-arm64/denver64/bionic/ |
| memset.S | 204 ldr zva_len, [tmp2, #:lo12:.Lcache_clear]
211 str zva_len, [tmp2, #:lo12:.Lcache_clear]
217 str zva_len, [tmp2, #:lo12:.Lcache_clear]
|
| /bionic/libc/arch-arm64/generic/bionic/ |
| memset.S | 177 ldr zva_len, [tmp2, #:lo12:.Lcache_clear]
184 str zva_len, [tmp2, #:lo12:.Lcache_clear]
190 str zva_len, [tmp2, #:lo12:.Lcache_clear]
|
| /frameworks/compile/mclinker/lib/Target/AArch64/ |
| AArch64PLT.h | 32 0x10, 0x02, 0x00, 0x91, /* add x16, x16, :lo12:PLTGOT + n * 8 */
|
| /external/llvm/test/MC/AArch64/ |
| inline-asm-modifiers.s | 10 add x0, x0, #:lo12:var_simple
|
| basic-a64-instructions.s | 350 // A relocation check (default to lo12, which is the only sane relocation anyway really)
351 add x0, x4, #:lo12:var
352 // CHECK: add x0, x4, :lo12:var // encoding: [0x80,0bAAAAAA00,0b00AAAAAA,0x91]
353 // CHECK: // fixup A - offset: 0, value: :lo12:var, kind: fixup_aarch64_add_imm12
[all...] |
| /external/valgrind/main/coregrind/m_dispatch/ |
| dispatch-arm64-linux.S | 180 add x1, x1, :lo12:VG_(stats__n_xindirs_32)
191 add x4, x4, :lo12:VG_(tt_fast) // x4 = &VG_(tt_fast)
207 add x1, x1, :lo12:VG_(stats__n_xindir_misses_32)
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | 357 unsigned Lo12 = Value & 0x0FFF;
359 // inst{11-0} = Lo12;
360 Value = (Hi4 << 16) | (Lo12);
[all...] |
| /external/valgrind/main/VEX/switchback/ |
| switchback.c | 470 " add x0, x0, :lo12:block" "\n"
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_Blur.S | 80 ifcc add \reg, \reg, #:lo12:1f
[all...] |
