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  /external/llvm/lib/Target/Mips/
MipsCodeEmitter.cpp 175 uint64_t TSFlags = MI.getDesc().TSFlags;
347 if (((MI->getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo) &&
MipsLongBranch.cpp 105 for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
226 for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) {
429 assert(I.Br->getDesc().getNumOperands() == 1);
MipsDelaySlotFiller.cpp 294 update(MI, 0, MI.getDesc().getNumOperands());
304 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
  /external/llvm/lib/Target/SystemZ/
SystemZElimCompare.cpp 241 unsigned CompareFlags = Compare->getDesc().TSFlags;
257 unsigned Flags = MI->getDesc().TSFlags;
SystemZInstrInfo.cpp 195 const MCInstrDesc &MCID = MI->getDesc();
488 bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
624 const MCInstrDesc &MCID = MI->getDesc();
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDGPUInstrInfo.cpp 229 return MI->getDesc().isPredicable();
  /external/llvm/lib/CodeGen/
CriticalAntiDepBreaker.cpp 184 if (i < MI->getDesc().getNumOperands())
185 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
308 if (i < MI->getDesc().getNumOperands())
309 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
MachineInstr.cpp 568 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
777 if (MII->getDesc().getFlags() & Mask) {
    [all...]
AggressiveAntiDepBreaker.cpp 387 if (i < MI->getDesc().getNumOperands())
388 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
471 if (i < MI->getDesc().getNumOperands())
472 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
    [all...]
MachineCSE.cpp 522 unsigned NumDefs = MI->getDesc().getNumDefs() +
523 MI->getDesc().getNumImplicitDefs();
  /external/llvm/lib/Target/ARM/
ARMBaseRegisterInfo.cpp 445 const MCInstrDesc &Desc = MI->getDesc();
635 const MCInstrDesc &Desc = MI->getDesc();
752 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
753 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
Thumb2ITBlockPass.cpp 142 const MCInstrDesc &MCID = MI->getDesc();
Thumb2SizeReduction.cpp 321 if (!HasImplicitCPSRDef(MI->getDesc()))
549 const MCInstrDesc &MCID = MI->getDesc();
698 const MCInstrDesc &MCID = MI->getDesc();
762 const MCInstrDesc &MCID = MI->getDesc();
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  /external/llvm/lib/Target/X86/
X86InstrBuilder.h 153 const MCInstrDesc &MCID = MI->getDesc();
  /external/mesa3d/src/gallium/drivers/radeon/
AMDGPUInstrInfo.cpp 229 return MI->getDesc().isPredicable();
  /packages/apps/TvSettings/Settings/src/com/android/tv/settings/device/apps/
AppManagementActivity.java 217 String description = actionType.getDesc(getResources());
  /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/
d3dx9effect.h 104 STDMETHOD(GetDesc)(THIS_ D3DXEFFECT_DESC* desc) PURE;
208 STDMETHOD(GetDesc)(THIS_ D3DXEFFECT_DESC* desc) PURE;
301 STDMETHOD(GetDesc)(THIS_ D3DXEFFECT_DESC* desc) PURE;
d3d9.h 355 STDMETHOD(GetDesc)(THIS_ D3DVOLUME_DESC* pDesc) PURE;
372 #define IDirect3DVolume9_GetDesc(p,a) (p)->lpVtbl->GetDesc(p,a)
386 #define IDirect3DVolume9_GetDesc(p,a) (p)->GetDesc(a)
513 STDMETHOD(GetDesc)(THIS_ D3DSURFACE_DESC* pDesc) PURE
    [all...]
  /external/llvm/include/llvm/CodeGen/
MachineInstr.h 264 /// getDesc - Returns the target instruction descriptor of this
266 const MCInstrDesc &getDesc() const { return *MCID; }
323 operands_begin(), operands_begin() + getDesc().getNumDefs());
327 operands_begin(), operands_begin() + getDesc().getNumDefs());
331 operands_begin() + getDesc().getNumDefs(), operands_end());
335 operands_begin() + getDesc().getNumDefs(), operands_end());
373 return getDesc().getFlags() & (1 << MCFlag);
    [all...]
LexicalScopes.h 57 const MDNode *getDesc() const { return Desc; }
  /external/chromium_org/content/common/gpu/media/
dxva_video_decode_accelerator.cc 301 HRESULT hr = dest_surface->GetDesc(&surface_desc);
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64LoadStoreOptimizer.cpp 649 TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
704 unsigned RegSize = TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
910 TII->getRegClass(MI->getDesc(), 0, TRI, *(MBB.getParent()))
    [all...]
  /external/llvm/lib/Target/MSP430/
MSP430InstrInfo.cpp 296 const MCInstrDesc &Desc = MI->getDesc();
  /external/llvm/lib/Target/R600/
AMDGPUInstrInfo.cpp 260 return MI->getDesc().isPredicable();
  /external/llvm/lib/Target/Hexagon/
HexagonNewValueJump.cpp 175 if (MII->getDesc().mayStore())
479 assert((MI->getDesc().isCompare()) &&

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