| /external/llvm/lib/Target/R600/ |
| SIRegisterInfo.h | 27 BitVector getReservedRegs(const MachineFunction &MF) const override;
30 MachineFunction &MF) const override;
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| AMDGPUAsmPrinter.cpp | 72 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
73 SetupMachineFunction(MF);
75 OutStreamer.emitRawComment(Twine('@') + MF.getName() + Twine(':'));
86 getSIProgramInfo(KernelInfo, MF);
87 EmitProgramInfoSI(MF, KernelInfo);
89 EmitProgramInfoR600(MF);
119 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
127 MF.dump();
148 void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
153 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>()
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUAsmPrinter.cpp | 40 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
43 MF.dump();
45 SetupMachineFunction(MF);
47 EmitProgramInfo(MF);
54 void AMDGPUAsmPrinter::EmitProgramInfo(MachineFunction &MF) {
61 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
124 SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();
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| SIRegisterInfo.h | 32 virtual BitVector getReservedRegs(const MachineFunction &MF) const;
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| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 211 MachineFunction *MF = Entry->getParent();
222 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
256 MachineFunction *MF = MI->getParent()->getParent();
257 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
262 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
268 I = MF->getRegInfo().livein_begin(),
269 E = MF->getRegInfo().livein_end(); I != E; ++I) {
276 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end()
[all...] |
| PPCRegisterInfo.cpp | 85 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
101 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
141 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
144 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
187 if (PPCFI->needsFP(MF))
190 if (hasBasePointer(MF))
199 if (PPCFI->needsFP(MF))
202 if (hasBasePointer(MF))
216 MachineFunction &MF) const {
217 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering()
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIRegisterInfo.h | 32 virtual BitVector getReservedRegs(const MachineFunction &MF) const;
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineFunctionPass.h | 39 virtual bool runOnMachineFunction(MachineFunction &MF) = 0;
|
| /external/llvm/lib/CodeGen/ |
| ErlangGC.cpp | 35 bool findCustomSafePoints(GCFunctionInfo &FI, MachineFunction &MF) override;
62 bool ErlangGC::findCustomSafePoints(GCFunctionInfo &FI, MachineFunction &MF) {
63 for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end(); BBI != BBE;
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| DFAPacketizer.cpp | 108 DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
116 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
118 ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) {
129 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
130 bool IsPostRA) : TM(MF.getTarget()), MF(MF) {
133 VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
|
| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.h | 55 MipsFunctionInfo(MachineFunction &MF)
56 : MF(MF), SRetReturnReg(0), GlobalBaseReg(0), Mips16SPAliasReg(0),
105 MachineFunction& MF;
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| MipsModuleISelDAGToDAG.h | 48 bool runOnMachineFunction(MachineFunction &MF) override;
|
| Mips16RegisterInfo.cpp | 48 (const MachineFunction &MF) const {
52 (const MachineFunction &MF) const {
57 (const MachineFunction &MF) const {
85 MachineFunction &MF = *MI.getParent()->getParent();
86 MachineFrameInfo *MFI = MF.getFrameInfo();
109 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
110 if (TFI->hasFP(MF)) {
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| Mips16ISelDAGToDAG.cpp | 39 bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
42 return MipsDAGToDAGISel::runOnMachineFunction(MF);
65 void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
66 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
71 MachineBasicBlock &MBB = MF.front();
73 MachineRegisterInfo &RegInfo = MF.getRegInfo();
74 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
97 void Mips16DAGToDAGISel::initMips16SPAliasReg(MachineFunction &MF) {
98 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
103 MachineBasicBlock &MBB = MF.front()
[all...] |
| /external/smack/src/org/xbill/DNS/ |
| MFRecord.java | 24 * Creates a new MF Record with the given data
29 super(name, Type.MF, dclass, ttl, mailAgent, "mail agent");
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64CleanupLocalDynamicTLSPass.cpp | 41 bool runOnMachineFunction(MachineFunction &MF) override {
42 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
94 MachineFunction *MF = I->getParent()->getParent();
96 static_cast<const AArch64TargetMachine *>(&MF->getTarget());
114 MachineFunction *MF = I->getParent()->getParent();
116 static_cast<const AArch64TargetMachine *>(&MF->getTarget());
120 MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 27 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
28 const MachineFrameInfo *FFI = MF.getFrameInfo();
37 return !MF.getFrameInfo()->hasVarSizedObjects();
52 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
55 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
57 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
58 if (!hasReservedCallFrame(MF)) {
85 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
86 MachineBasicBlock &MBB = MF.front();
88 MachineFrameInfo *MFI = MF.getFrameInfo()
[all...] |
| ARMFrameLowering.cpp | 49 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
50 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
56 const MachineFrameInfo *MFI = MF.getFrameInfo();
58 return ((MF.getTarget().Options.DisableFramePointerElim(MF) &&
60 RegInfo->needsStackRealignment(MF) ||
70 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
71 const MachineFrameInfo *FFI = MF.getFrameInfo();
80 return !MF.getFrameInfo()->hasVarSizedObjects();
88 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const
[all...] |
| Thumb1InstrInfo.cpp | 65 MachineFunction &MF = *MBB.getParent();
66 MachineFrameInfo &MFI = *MF.getFrameInfo();
68 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
93 MachineFunction &MF = *MBB.getParent();
94 MachineFrameInfo &MFI = *MF.getFrameInfo();
96 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXRegisterInfo.cpp | 82 NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
87 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
100 MachineFunction &MF = *MI.getParent()->getParent();
101 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
109 unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
| NVPTXReplaceImageHandles.cpp | 35 bool runOnMachineFunction(MachineFunction &MF) override;
38 void replaceImageHandle(MachineOperand &Op, MachineFunction &MF);
47 bool NVPTXReplaceImageHandles::runOnMachineFunction(MachineFunction &MF) {
51 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
73 MachineFunction &MF = *MI.getParent()->getParent();
122 replaceImageHandle(TexHandle, MF);
123 replaceImageHandle(SampHandle, MF);
145 replaceImageHandle(SurfHandle, MF);
167 replaceImageHandle(SurfHandle, MF);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 42 SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
56 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
90 SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
95 static void replaceFI(MachineFunction &MF,
111 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
162 MachineFunction &MF = *MI.getParent()->getParent();
163 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
166 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
171 int stackSize = MF.getFrameInfo()->getStackSize();
177 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo()
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 177 MachineFunction *MF = MBB.getParent();
178 const MachineFrameInfo &MFI = *MF->getFrameInfo();
180 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex),
217 bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const {
218 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
219 MF.getFrameInfo()->hasVarSizedObjects();
222 void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
223 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
225 MachineFrameInfo *MFI = MF.getFrameInfo()
[all...] |
| XCoreRegisterInfo.cpp | 205 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
206 return MF.getMMI().hasDebugInfo() ||
207 MF.getFunction()->needsUnwindTableEntry();
210 const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
224 const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
225 if (TFI->hasFP(*MF))
230 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
232 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
238 if (TFI->hasFP(MF)) {
245 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 181 /// registers from this register class in MF. The raw order comes directly
194 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
195 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
319 BitVector getAllocatableSet(const MachineFunction &MF,
424 getCalleeSavedRegs(const MachineFunction *MF = nullptr) const = 0;
453 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
574 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
606 MachineFunction &MF) const {
653 const MachineFunction &MF,
671 MachineFunction &MF) const
[all...] |
