| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 104 getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
118 BitVector getReservedRegs(const MachineFunction &MF) const override;
121 getPointerRegClass(const MachineFunction &MF,
130 MachineFunction &MF) const override;
135 const MachineFunction &MF,
139 MachineFunction &MF) const override;
143 bool hasBasePointer(const MachineFunction &MF) const;
145 bool canRealignStack(const MachineFunction &MF) const;
146 bool needsStackRealignment(const MachineFunction &MF) const override;
158 bool cannotEliminateFrame(const MachineFunction &MF) const
[all...] |
| Thumb2RegisterInfo.cpp | 42 MachineFunction &MF = *MBB.getParent();
43 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
44 MachineConstantPool *ConstantPool = MF.getConstantPool();
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
45 virtual bool runOnMachineFunction(MachineFunction &MF);
67 bool SIAssignInterpRegsPass::runOnMachineFunction(MachineFunction &MF)
89 SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();
90 MachineRegisterInfo &MRI = MF.getRegInfo();
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
122 void SIAssignInterpRegsPass::AddLiveIn(MachineFunction * MF,
129 MF->front().addLiveIn(physReg);
130 BuildMI(MF->front(), MF->front().begin(), DebugLoc()
[all...] |
| AMDGPUAsmPrinter.cpp | 40 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
43 MF.dump();
45 SetupMachineFunction(MF);
47 EmitProgramInfo(MF);
54 void AMDGPUAsmPrinter::EmitProgramInfo(MachineFunction &MF) {
61 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
124 SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
45 virtual bool runOnMachineFunction(MachineFunction &MF);
67 bool SIAssignInterpRegsPass::runOnMachineFunction(MachineFunction &MF)
89 SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();
90 MachineRegisterInfo &MRI = MF.getRegInfo();
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
122 void SIAssignInterpRegsPass::AddLiveIn(MachineFunction * MF,
129 MF->front().addLiveIn(physReg);
130 BuildMI(MF->front(), MF->front().begin(), DebugLoc()
[all...] |
| /external/llvm/lib/CodeGen/ |
| StackMapLivenessAnalysis.cpp | 69 MF = &_MF;
70 TRI = MF->getTarget().getRegisterInfo();
74 if (!MF->getFrameInfo()->hasPatchPoint()) {
85 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
115 MI.addOperand(*MF, MO);
122 uint32_t *Mask = MF->allocateRegisterMask(TRI->getNumRegs());
|
| ExpandISelPseudos.cpp | 34 bool runOnMachineFunction(MachineFunction &MF) override;
47 bool ExpandISelPseudos::runOnMachineFunction(MachineFunction &MF) {
49 const TargetLowering *TLI = MF.getTarget().getTargetLowering();
52 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
|
| AllocationOrder.cpp | 34 const MachineFunction &MF = VRM.getMachineFunction();
36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
|
| EdgeBundles.cpp | 39 bool EdgeBundles::runOnMachineFunction(MachineFunction &mf) {
40 MF = &mf;
42 EC.grow(2 * MF->getNumBlockIDs());
44 for (const auto &MBB : *MF) {
59 for (unsigned i = 0, e = MF->getNumBlockIDs(); i != e; ++i) {
76 const MachineFunction *MF = G.getMachineFunction();
79 for (const auto &MBB : *MF) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFixupHwLoops.cpp | 43 bool runOnMachineFunction(MachineFunction &MF) override;
62 bool fixupLoopInstrs(MachineFunction &MF);
65 void convertLoopInstr(MachineFunction &MF,
89 bool HexagonFixupHwLoops::runOnMachineFunction(MachineFunction &MF) {
90 bool Changed = fixupLoopInstrs(MF);
103 bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) {
111 for (MachineFunction::iterator MBB = MF.begin(), MBBe = MF.end();
124 for (MachineFunction::iterator MBB = MF.begin(), MBBe = MF.end()
[all...] |
| HexagonFrameLowering.cpp | 46 void HexagonFrameLowering::determineFrameLayout(MachineFunction &MF) const {
47 MachineFrameInfo *MFI = MF.getFrameInfo();
53 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
76 void HexagonFrameLowering::emitPrologue(MachineFunction &MF) const {
77 MachineBasicBlock &MBB = MF.front();
78 MachineFrameInfo *MFI = MF.getFrameInfo();
81 static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo());
83 determineFrameLayout(MF);
96 MF.getInfo<HexagonMachineFunctionInfo>();
114 if (hasFP(MF)) {
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 26 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
36 SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
38 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
40 if (TFI->hasFP(MF)) {
63 MachineFunction &MF = *MBB.getParent();
65 static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
66 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
71 unsigned BasePtr = getFrameRegister(MF);
72 int64_t Offset = (TFI->getFrameIndexOffset(MF, FrameIndex) +
101 MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass)
[all...] |
| SystemZInstrBuilder.h | 29 MachineFunction &MF = *MI->getParent()->getParent();
30 MachineFrameInfo *MFFrame = MF.getFrameInfo();
39 MF.getMachineMemOperand(MachinePointerInfo(
|
| SystemZFrameLowering.cpp | 64 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
66 MachineFrameInfo *MFFrame = MF.getFrameInfo();
67 MachineRegisterInfo &MRI = MF.getRegInfo();
68 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
69 bool HasFP = hasFP(MF);
70 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
71 bool IsVarArg = MF.getFunction()->isVarArg();
95 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
129 MachineFunction &MF = *MBB.getParent();
130 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 51 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
58 MachineFunction &MF) const {
65 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
66 return 28 - TFI->hasFP(MF);
83 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
127 getReservedRegs(const MachineFunction &MF) const {
164 if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
195 const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
200 if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2()
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreMachineFunctionInfo.h | 52 explicit XCoreFunctionInfo(MachineFunction &MF) :
65 int createLRSpillSlot(MachineFunction &MF);
72 int createFPSpillSlot(MachineFunction &MF);
79 const int* createEHSpillSlot(MachineFunction &MF);
97 bool isLargeFrame(const MachineFunction &MF) const;
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 39 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
40 return !MF.getFrameInfo()->hasVarSizedObjects();
46 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
47 const MachineFrameInfo *MFI = MF.getFrameInfo();
48 const MachineModuleInfo &MMI = MF.getMMI();
49 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
51 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
52 RegInfo->needsStackRealignment(MF) ||
55 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() |
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 42 static unsigned estimateStackSize(MachineFunction &MF) {
43 const MachineFrameInfo *FFI = MF.getFrameInfo();
62 bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const {
67 if (MF.getFunction()->getAttributes().hasAttribute(
71 const MachineFrameInfo *MFI = MF.getFrameInfo();
72 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
78 if (MFI->hasCalls() || hasFP(MF) || NumBytes > 128)
85 bool AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
86 const MachineFrameInfo *MFI = MF.getFrameInfo();
89 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo()
[all...] |
| AArch64StorePairSuppress.cpp | 33 MachineFunction *MF;
119 bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &mf) {
120 MF = &mf;
121 TII = static_cast<const AArch64InstrInfo *>(MF->getTarget().getInstrInfo());
122 TRI = MF->getTarget().getRegisterInfo();
123 MRI = &MF->getRegInfo();
125 MF->getTarget().getSubtarget<TargetSubtargetInfo>();
131 DEBUG(dbgs() << "*** " << getPassName() << ": " << MF->getName() << '\n');
142 for (auto &MBB : *MF) {
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| CalcSpillWeights.h | 50 MachineFunction &MF;
58 VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis,
62 : MF(mf), LIS(lis), Loops(loops), MBFI(mbfi), normalize(norm) {}
70 void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF,
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfException.h | 52 void beginFunction(const MachineFunction *MF) override;
79 void beginFunction(const MachineFunction *MF) override;
111 void beginFunction(const MachineFunction *MF) override;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXRegisterInfo.h | 45 getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
47 BitVector getReservedRegs(const MachineFunction &MF) const override;
53 unsigned getFrameRegister(const MachineFunction &MF) const override;
|
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRLiveRanges.cpp | 43 virtual bool runOnMachineFunction(MachineFunction &MF) override;
74 bool SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction &MF) {
75 MachineRegisterInfo &MRI = MF.getRegInfo();
77 MF.getTarget().getRegisterInfo());
80 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
|
| /external/clang/test/Layout/ |
| ms-x86-member-pointers.cpp | 13 struct MF { char a; int (M::*mp)(); };
53 // CHECK-NEXT: 0 | struct MF
78 sizeof(MF) +
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 39 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
40 const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
41 const Function* F = MF->getFunction();
65 if (TFI->hasFP(*MF))
74 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
76 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
89 if (TFI->hasFP(MF)) {
98 MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
111 MachineFunction &MF = *MBB.getParent();
112 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering()
[all...] |
