| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 143 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
147 Op0.getValueType(), Op0, Op1, Op2);
174 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
176 Op0, DAG.getValueType(NewVT),
177 DAG.getValueType(Op0.getValueType()),
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/IR/ |
| Instructions.cpp | 62 const char *SelectInst::areInvalidOperands(Value *Op0, Value *Op1, Value *Op2) {
66 if (VectorType *VT = dyn_cast<VectorType>(Op0->getType())) {
68 if (VT->getElementType() != Type::getInt1Ty(Op0->getContext()))
76 } else if (Op0->getType() != Type::getInt1Ty(Op0->getContext())) {
[all...] |
| Verifier.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombine.h | 179 Instruction *FoldShiftByConstant(Value *Op0, Constant *Op1,
|
| InstCombineVectorOps.cpp | 30 if (Constant *Op0 = C->getAggregateElement(0U)) {
33 if (C->getAggregateElement(i) != Op0)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| AArch64FastISel.cpp | 691 Value *Op0 = I->getOperand(0);
695 if (!isLoadStoreTypeLegal(Op0->getType(), VT) ||
700 unsigned SrcReg = getRegForValue(Op0);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 847 SDValue OP0;
857 OP0 = Sext0;
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| LoopStrengthReduce.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| SLPVectorizer.cpp | [all...] |
| LoopVectorize.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
