| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 207 SmallVector<unsigned, 8> Ops;
208 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
211 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/IR/ |
| InstrTypes.h | 38 Use *Ops, unsigned NumOps,
40 : Instruction(Ty, iType, Ops, NumOps, InsertBefore) {}
43 Use *Ops, unsigned NumOps, BasicBlock *InsertAtEnd)
44 : Instruction(Ty, iType, Ops, NumOps, InsertAtEnd) {}
[all...] |
| Constants.h | 802 ConstantExpr(Type *ty, unsigned Opcode, Use *Ops, unsigned NumOps)
803 : Constant(ty, ConstantExprVal, Ops, NumOps) {
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 122 const SmallVectorImpl<unsigned> &Ops,
|
| AArch64ISelLowering.cpp | 220 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 577 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
580 makeArrayRef(Ops, Op0->getNumOperands()));
[all...] |
| Mips16ISelDAGToDAG.cpp | 273 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
281 SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops);
|
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/IR/ |
| Module.cpp | 314 Value *Ops[3] = {
317 getOrInsertModuleFlagsMetadata()->addOperand(MDNode::get(Context, Ops));
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 304 const SmallVectorImpl<unsigned> &Ops,
312 const SmallVectorImpl<unsigned> &Ops,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 463 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
465 DAG.getVTList(ValueVTs), Ops);
[all...] |
| FunctionLoweringInfo.cpp | 122 std::vector<TargetLowering::AsmOperandInfo> Ops =
124 for (size_t I = 0, E = Ops.size(); I != E; ++I) {
125 TargetLowering::AsmOperandInfo &Op = Ops[I];
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 749 const SmallVectorImpl<unsigned> &Ops,
755 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
768 if (Ops.size() != 1)
771 unsigned OpNum = Ops[0];
866 const SmallVectorImpl<unsigned> &Ops,
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| ArgumentPromotion.cpp | 691 std::vector<Value*> Ops;
697 Ops.reserve(SI->size());
706 Ops.push_back(ConstantInt::get(IdxTy, *II));
711 V = GetElementPtrInst::Create(V, Ops, V->getName()+".idx", Call);
712 Ops.clear();
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcherGen.cpp | 773 // 'default ops' operands.
[all...] |
| /external/llvm/lib/Analysis/ |
| TypeBasedAliasAnalysis.cpp | 611 Value *Ops[3] = { Ret, Ret, ConstantInt::get(Int64, 0) };
612 return MDNode::get(A->getContext(), Ops);
|
| /external/llvm/lib/Target/R600/ |
| R600Packetizer.cpp | 134 unsigned Ops[] = {
140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 137 // We do not currently implement these libm ops for PowerPC.
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 707 SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
720 MVT::Other, Ops);
733 SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
746 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
797 SDValue Ops[] = {SDValue(NewBase,0),
802 MVT::Other, Ops);
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| InstructionSimplify.h | 194 Value *SimplifyGEPInst(ArrayRef<Value *> Ops, const DataLayout *TD = nullptr,
|
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 421 bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
|
