| /external/antlr/antlr-3.4/runtime/Delphi/Sources/Antlr3.Runtime.Tests/ |
| Antlr.Runtime.Tree.Tests.pas | 208 R0: ICommonTree;
211 R0 := TCommonTree.Create(TCommonToken.Create(101));
212 R0.AddChild(TCommonTree.Create(TCommonToken.Create(102)));
213 R0.GetChild(0).AddChild(TCommonTree.Create(TCommonToken.Create(103)));
214 R0.AddChild(TCommonTree.Create(TCommonToken.Create(104)));
215 CheckNull(R0.Parent);
216 CheckEquals(R0.ChildIndex,-1);
221 Root, R0, C0, C1, C2: ICommonTree;
229 R0 := TCommonTree.Create(IToken(nil));
233 R0.AddChild(C0)
[all...] |
| /art/runtime/arch/arm/ |
| registers_arm.h | 27 R0 = 0,
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_gs.h | 81 struct brw_reg R0;
|
| brw_clip_util.c | 227 brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
237 allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
239 c->reg.R0,
263 c->reg.R0,
344 struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
377 c->reg.R0,
379 c->reg.R0,
|
| brw_gs_emit.c | 63 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
90 * Set up the initial value of c->reg.header register based on c->reg.R0.
92 * The following information is passed to the GS thread in R0, and needs to be
101 * R0 to the header register.
106 brw_MOV(p, c->reg.header, c->reg.R0);
124 * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
134 brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
403 get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
466 /* Now, reinitialize the header register from R0 to restore the parts of
514 get_element_ud(c->reg.R0, 2)
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_gs.h | 81 struct brw_reg R0;
|
| brw_clip_util.c | 227 brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
237 allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
239 c->reg.R0,
263 c->reg.R0,
344 struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
377 c->reg.R0,
379 c->reg.R0,
|
| brw_gs_emit.c | 63 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
90 * Set up the initial value of c->reg.header register based on c->reg.R0.
92 * The following information is passed to the GS thread in R0, and needs to be
101 * R0 to the header register.
106 brw_MOV(p, c->reg.header, c->reg.R0);
124 * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
134 brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
403 get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
466 /* Now, reinitialize the header register from R0 to restore the parts of
514 get_element_ud(c->reg.R0, 2)
[all...] |
| /art/compiler/utils/arm/ |
| managed_register_arm_test.cc | 31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0);
37 EXPECT_EQ(R0, reg.AsCoreRegister());
235 EXPECT_EQ(R0, reg.AsRegisterPairLow());
237 EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromCoreRegisterPair(R0)));
292 EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromCoreRegister(R0)));
298 ArmManagedRegister reg_R0 = ArmManagedRegister::FromCoreRegister(R0);
300 EXPECT_TRUE(reg_R0.Equals(ArmManagedRegister::FromCoreRegister(R0)));
308 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromCoreRegister(R0)));
318 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromCoreRegister(R0)));
328 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromCoreRegister(R0)));
[all...] |
| /external/mdnsresponder/mDNSCore/ |
| DNSDigest.c | 895 #define R0(a,b,c,d,k,s,t) { \
952 R0(A,B,C,D,X[ 0], 7,0xd76aa478L);
953 R0(D,A,B,C,X[ 1],12,0xe8c7b756L);
954 R0(C,D,A,B,X[ 2],17,0x242070dbL);
955 R0(B,C,D,A,X[ 3],22,0xc1bdceeeL);
956 R0(A,B,C,D,X[ 4], 7,0xf57c0fafL);
957 R0(D,A,B,C,X[ 5],12,0x4787c62aL);
958 R0(C,D,A,B,X[ 6],17,0xa8304613L);
959 R0(B,C,D,A,X[ 7],22,0xfd469501L);
960 R0(A,B,C,D,X[ 8], 7,0x698098d8L)
[all...] |
| /bionic/libc/upstream-netbsd/common/lib/libc/hash/sha1/ |
| sha1.c | 65 * (R0+R1), R2, R3, R4 are the different operations (rounds) used in SHA1
67 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30);
100 #define nR0(v,w,x,y,z,i) R0(*v,*w,*x,*y,*z,i)
183 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
184 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7)
[all...] |
| /external/libhevc/decoder/arm/ |
| ihevcd_fmt_conv_420sp_to_rgba8888.s | 56 @* Arguments : R0 pubY *
69 @* Register Usage : R0 - R14 *
94 @//R0 - Y PTR
110 @PLD [R0]
152 ADD R7,R0,R6 @// luma_next_row = luma + luma_stride
166 VLD2.8 {D30,D31},[R0]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row 1
188 @PLD [R0]
269 VLD2.8 {D30,D31},[R0]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row 1
274 PLD [R0]
431 ADD R0,R7,R10 @// luma = luma_next + offse
[all...] |
| /external/qemu/distrib/ext4_utils/src/ |
| sha1.c | 51 * (R0+R1), R2, R3, R4 are the different operations (rounds) used in SHA1
53 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30);
76 #define nR0(v,w,x,y,z,i) R0(*v,*w,*x,*y,*z,i)
161 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
162 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7)
[all...] |
| /system/extras/ext4_utils/ |
| sha1.c | 51 * (R0+R1), R2, R3, R4 are the different operations (rounds) used in SHA1
53 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30);
76 #define nR0(v,w,x,y,z,i) R0(*v,*w,*x,*y,*z,i)
161 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
162 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7)
[all...] |
| /external/chromium_org/third_party/openssl/openssl/crypto/md5/asm/ |
| md5-586-mac.S | 24 # R0 section
27 # R0 0
37 # R0 1
47 # R0 2
57 # R0 3
67 # R0 4
77 # R0 5
87 # R0 6
97 # R0 7
107 # R0 8
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCTargetDesc.cpp | 45 InitHexagonMCRegisterInfo(X, Hexagon::R0);
|
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
76 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
126 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
|
| ARMInstrInfo.cpp | 45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
46 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/lc3b/tests/ |
| lc3b-mp22NC.asm | 4 DONTBR: LEA R0, AA
7 LD R7, R0, ADATA3F-AA
22 LD R7, R0, ADATA39-AA
38 LD R7, R0, ADATA36-AA
42 LD R7, R0, ADATA37-AA
50 LOOP: LD R7, R0, ADATA32-AA
62 ST R7, R0, ADATA8-AA
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVarargsCallingConvention.h | 53 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
109 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
|
| /libcore/luni/src/test/java/libcore/java/lang/ |
| ClassCastExceptionTest.java | 81 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
86 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
|
| /external/chromium_org/third_party/openssl/openssl/crypto/md4/ |
| md4_locl.h | 102 #define R0(a,b,c,d,k,s,t) { \
|
| /external/openssl/crypto/md4/ |
| md4_locl.h | 102 #define R0(a,b,c,d,k,s,t) { \
|
| /external/valgrind/main/VEX/priv/ |
| host_s390_defs.c | 77 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
122 - 1 /* r0 */
649 volatile registers are: r0 - r5. Valgrind's register allocator
650 does not know about r0, so we can leave that out */
[all...] |
| /external/eigen/Eigen/src/Core/products/ |
| GeneralBlockPanelKernel.h | 580 ResScalar* r0 = &res[(j2+0)*resStride + i]; local
581 ResScalar* r1 = r0 + resStride;
585 prefetch(r0+16);
757 ResPacket R0, R1, R2, R3, R4, R5, R6;
760 R0 = ploadu<ResPacket>(r0);
764 R4 = ploadu<ResPacket>(r0 + ResPacketSize);
767 traits.acc(C0, alphav, R0);
768 pstoreu(r0, R0);
938 ResScalar* r0 = &res[(j2+0)*resStride + i]; local
1043 ResScalar* r0 = &res[(j2+0)*resStride + i]; local
[all...] |
