| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 33 const TargetInstrInfo *TII;
102 MI->setDesc(TII->get(TargetOpcode::KILL));
113 MI->setDesc(TII->get(TargetOpcode::KILL));
121 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
140 MI->setDesc(TII->get(TargetOpcode::KILL));
155 MI->setDesc(TII->get(TargetOpcode::KILL));
165 TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
186 TII = MF.getTarget().getInstrInfo();
203 if (TII->expandPostRAPseudo(MI)) {
|
| ErlangGC.cpp | 56 const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
58 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
|
| BranchFolding.cpp | 156 if (!TII->isUnpredicatedTerminator(I))
183 const TargetInstrInfo *tii,
186 if (!tii) return false;
190 TII = tii;
207 if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true))
405 TII->ReplaceTailWithBranchTo(OldInst, NewDest);
419 if (!TII->isLegalToSplitMBBAt(CurMBB, BBI1))
467 const TargetInstrInfo *TII) {
474 !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true))
[all...] |
| IfConversion.cpp | 162 const TargetInstrInfo *TII;
219 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra,
229 TII->isProfitableToIfCvt(TBB, TCycle, TExtra, FBB, FCycle, FExtra,
273 TII = MF.getTarget().getInstrInfo();
280 SchedModel.init(*ST.getSchedModel(), &ST, TII);
282 if (!TII) return false;
290 BFChange = BF.OptimizeFunction(MF, TII,
424 BF.OptimizeFunction(MF, TII,
450 if (!TII->ReverseBranchCondition(BBI.BrCond)) {
451 TII->RemoveBranch(*BBI.BB)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64CleanupLocalDynamicTLSPass.cpp | 97 const AArch64InstrInfo *TII = TM->getInstrInfo();
102 TII->get(TargetOpcode::COPY),
117 const AArch64InstrInfo *TII = TM->getInstrInfo();
126 TII->get(TargetOpcode::COPY),
|
| AArch64ExpandPseudoInsts.cpp | 30 const AArch64InstrInfo *TII;
90 const AArch64InstrInfo *TII, unsigned ChunkIdx) {
98 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
108 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
141 const AArch64InstrInfo *TII) {
165 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
185 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
210 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
275 const AArch64InstrInfo *TII) {
348 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)
[all...] |
| AArch64BranchRelaxation.cpp | 80 const AArch64InstrInfo *TII;
168 Size += TII->GetInstSizeInBytes(&MI);
186 Offset += TII->GetInstSizeInBytes(I);
229 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::B)).addMBB(NewBB);
396 MI->setDesc(TII->get(getOppositeConditionOpcode(MI->getOpcode())));
408 TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, false);
413 int delta = TII->GetInstSizeInBytes(&MBB->back());
431 MBB, DebugLoc(), TII->get(getOppositeConditionOpcode(MI->getOpcode())))
439 BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
440 BuildMI(MBB, DebugLoc(), TII->get(AArch64::B)).addMBB(DestBB)
[all...] |
| AArch64AdvSIMDScalarPass.cpp | 66 const AArch64InstrInfo *TII;
264 static MachineInstr *insertCopy(const AArch64InstrInfo *TII, MachineInstr *MI,
267 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AArch64::COPY),
322 insertCopy(TII, MI, Src0, OrigSrc0, true);
327 insertCopy(TII, MI, Src1, OrigSrc1, true);
338 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst)
345 insertCopy(TII, MI, MI->getOperand(0).getReg(), Dst, true);
374 TII = static_cast<const AArch64InstrInfo *>(TM.getInstrInfo());
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPURegisterInfo.h | 33 const TargetInstrInfo &TII;
36 AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
|
| SIRegisterInfo.cpp | 21 const TargetInstrInfo &tii)
22 : AMDGPURegisterInfo(tm, tii),
24 TII(tii)
|
| SIISelLowering.cpp | 28 TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo()))
68 const TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
72 if (TII->get(MI->getOpcode()).TSFlags & SIInstrFlags::NEED_WAIT) {
82 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
97 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
112 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
145 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WAITCNT))
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
164 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp)
170 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32)
[all...] |
| R600ISelLowering.h | 32 const R600InstrInfo * TII;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 281 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
308 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
312 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
316 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
333 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
338 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
344 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
348 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
358 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
363 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg
[all...] |
| PPCFrameLowering.cpp | 255 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
325 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
499 const PPCInstrInfo &TII =
523 HandleVRSaveUpdate(MBBI, TII);
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 30 TII = static_cast<const R600InstrInfo*>(DAG->TII);
37 InstKindLimit[IDAlu] = TII->getMaxAlusPerClause();
223 if (TII->isTransOnly(MI))
246 if(TII->isVector(*MI) ||
247 TII->isCubeOp(MI->getOpcode()) ||
248 TII->isReductionOp(MI->getOpcode()) ||
253 if (TII->isLDSInstr(MI->getOpcode())) {
287 if (TII->readsLDSSrcReg(MI))
297 if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode)
[all...] |
| R600MachineScheduler.h | 30 const R600InstrInfo *TII;
71 DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
|
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 113 const TargetInstrInfo *TII = TM.getInstrInfo();
130 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
148 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
158 TII->get(SP::UNIMP)).addImm(structSize);
362 const TargetInstrInfo *TII)
377 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
389 const TargetInstrInfo *TII)
416 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
428 const TargetInstrInfo *TII)
453 RestoreMI->setDesc(TII->get(SP::RESTOREri))
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSERegisterInfo.cpp | 173 const MipsSEInstrInfo &TII =
176 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
188 const MipsSEInstrInfo &TII =
191 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
193 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZShortenInst.cpp | 40 const SystemZInstrInfo *TII;
56 : MachineFunctionPass(ID), TII(nullptr), LowGPRs(), HighGPRs() {
87 MI.setDesc(TII->get(LLIxL));
92 MI.setDesc(TII->get(LLIxH));
153 TII = static_cast<const SystemZInstrInfo *>(F.getTarget().getInstrInfo());
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 28 TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo()))
68 const TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
72 if (TII->get(MI->getOpcode()).TSFlags & SIInstrFlags::NEED_WAIT) {
82 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
97 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
112 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
145 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WAITCNT))
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
164 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp)
170 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32)
[all...] |
| R600ISelLowering.h | 32 const R600InstrInfo * TII;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCopyToCombine.cpp | 59 const HexagonInstrInfo *TII;
114 const HexagonInstrInfo *TII,
363 if(TII->mayBeNewStore(MI)) {
378 if (!isCombinableInstType(DefInst, TII, ShouldCombineAggressively))
421 TII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo());
444 if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
477 if (!isCombinableInstType(I2, TII, ShouldCombineAggressively))
566 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ii), DoubleDestReg)
573 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_iI_V4), DoubleDestReg)
583 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ii), DoubleDestReg
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineSSAUpdater.h | 54 const TargetInstrInfo *TII;
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.h | 49 const ARMBaseInstrInfo &TII) const;
|
| Thumb2InstrInfo.cpp | 216 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
218 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
235 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
241 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
250 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
256 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
271 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
283 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
322 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
439 const ARMBaseInstrInfo &TII) {
[all...] |
