| /bionic/libc/arch-mips/bionic/ |
| _setjmp.S | 79 s.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
123 l.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
|
| setjmp.S | 92 s.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
154 l.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
|
| /bionic/libc/arch-mips64/bionic/ |
| _setjmp.S | 79 s.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
123 l.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
|
| setjmp.S | 92 s.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
154 l.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
|
| /external/valgrind/main/none/tests/mips32/ |
| MoveIns.c | 307 TESTINSNMOVE("mfc1 $t9, $f24", 28, f24, t9);
336 TESTINSNMOVEt("mtc1 $t9, $f24", 30, f24, t9);
365 TESTINSNMOVE1s("mov.s $f23, $f24", 28, f23, f24);
366 TESTINSNMOVE1s("mov.s $f24, $f25", 32, f24, f25);
393 TESTINSNMOVE1d("mov.d $f22, $f24", 40, f22, f24);
[all...] |
| /external/llvm/test/MC/ELF/ |
| cfi.s | 143 f24: label
|
| /external/llvm/test/MC/Mips/mips1/ |
| valid.s | 10 add.s $f8,$f21,$f24
35 cvt.w.s $f20,$f24
|
| invalid-mips5-wrong-error.s | 45 puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 28 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
36 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| valid.s | 10 add.s $f8,$f21,$f24
40 cvt.l.d $f24,$f15
46 cvt.w.s $f20,$f24
|
| /external/llvm/test/MC/PowerPC/ |
| ppc64-regs.s | 64 #CHECK: .cfi_offset f24, 500
181 .cfi_offset f24,500
|
| /external/oprofile/module/ia64/ |
| IA64entry.h | 47 .spillsp f24, SW(F24)+16+(off); .spillsp f25, SW(F25)+16+(off); \
|
| oprofile_stubs.S | 117 ldf.fill f23=[sp]; ldf.fill f24=[sp]; mov f25=f0
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 12 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
28 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
56 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5-wrong-error.s | 45 puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 10 add.s $f8,$f21,$f24
42 cvt.l.d $f24,$f15
48 cvt.w.s $f20,$f24
143 mfhc1 $s8,$f24
186 nmsub.s $f1,$f24,$f19,$f4
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 10 add.s $f8,$f21,$f24
38 cvt.l.d $f24,$f15
44 cvt.w.s $f20,$f24
|
| invalid-mips5-wrong-error.s | 45 puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 10 add.s $f8,$f21,$f24
40 cvt.l.d $f24,$f15
46 cvt.w.s $f20,$f24
|
| invalid-mips5-wrong-error.s | 45 puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 10 add.s $f8,$f21,$f24
42 cvt.l.d $f24,$f15
48 cvt.w.s $f20,$f24
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips5-wrong-error.s | 47 puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/chromium_org/third_party/mesa/src/src/mesa/sparc/ |
| sparc_matrix.h | 43 #define M8 %f24
|
| /external/chromium_org/third_party/openssl/openssl/crypto/bn/asm/ |
| ppc64-mont.pl | 153 $T0a="f24"; $T0b="f25";
234 stfd f24,`-8*8`($i)
1079 lfd f24,`-8*8`($i)
|
| /external/chromium_org/third_party/openssl/openssl/crypto/ |
| ia64cpuid.S | 115 { .mfi; mov f24=f0 }
|
