| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 179 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
249 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
270 && I->getOpcode() != SP::BCOND
|
| SparcCodeEmitter.cpp | 240 case SP::BCOND:
|
| SparcInstrAliases.td | 68 (BCOND brtarget:$imm, condVal)>;
|
| SparcInstrInfo.td | 631 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
[all...] |
| SparcISelLowering.cpp | [all...] |
| /external/qemu/target-mips/ |
| machine.c | 86 i = env->bcond;
238 env->bcond = i;
|
| translate.c | 431 static TCGv cpu_dspctrl, btarget, bcond; variable
[all...] |
| cpu.h | 457 target_ulong bcond; /* Branch condition (if needed) */ member in struct:CPUMIPSState
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.td | [all...] |
| /external/kernel-headers/original/uapi/asm-mips/asm/ |
| inst.h | 83 * rt field of bcond opcodes.
|
| /system/core/libpixelflinger/codeflinger/ |
| mips_disassem.c | 69 /* 0 */ "spec", "bcond","j ", "jal", "beq", "bne", "blez", "bgtz",
|
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-arm64.cc | [all...] |
