| /external/llvm/test/MC/AArch64/ |
| arm64-verbose-vector-case.s | 3 pmull v8.8h, v8.8b, v8.8b label
5 pmull v8.1q, v8.1d, v8.1d label
7 // CHECK: pmull v8.8h, v8.8b, v8.8b // encoding: [0x08,0xe1,0x28,0x0e]
9 // CHECK: pmull v8.1q, v8.1d, v8.1d // encoding: [0x08,0xe1,0xe8,0x0e]
12 pmull v8.8H, v8.8B, v8.8B label
14 pmull v8.1Q, v8.1D, v8.1D label
16 // CHECK: pmull v8.8h, v8.8b, v8.8b // encoding: [0x08,0xe1,0x28,0x0e]
18 // CHECK: pmull v8.1q, v8.1d, v8.1d // encoding: [0x08,0xe1,0xe8,0x0e]
|
| arm64-diagno-predicate.s | 15 pmull v0.1q, v1.1d, v2.1d
17 // CHECK-ERROR-NEXT: pmull v0.1q, v1.1d, v2.1d
|
| neon-3vdiff.s | 285 pmull v0.8h, v1.8b, v2.8b
286 pmull v0.1q, v1.1d, v2.1d
288 // CHECK: pmull v0.8h, v1.8b, v2.8b // encoding: [0x20,0xe0,0x22,0x0e]
289 // CHECK: pmull v0.1q, v1.1d, v2.1d // encoding: [0x20,0xe0,0xe2,0x0e]
|
| arm64-advsimd.s | [all...] |
| neon-diagnostics.s | [all...] |
| /external/openssl/crypto/modes/asm/ |
| ghashv8-armx.S | 79 .byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.lo·Xi.lo
83 .byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
91 .byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase
102 .byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
|
| ghashv8-armx-64.S | 78 pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo
82 pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)
90 pmull v18.1q,v0.1d,v19.1d //1st phase
101 pmull v0.1q,v0.1d,v19.1d
|
| ghashv8-armx.pl | 21 # PMULL[2] 32-bit NEON(*)
189 m/\.p64/o and s/\.16b/\.1q/o; # 1st pmull argument
190 m/l\.p64/o and s/\.16b/\.1d/go; # 2nd and 3rd pmull arguments
|
| /external/openssl/crypto/ |
| arm64cpuid.S | 44 pmull v0.1q, v0.1d, v0.1d
|
| /external/clang/test/CodeGen/ |
| aarch64-poly128.c | 40 // CHECK: pmull {{v[0-9]+}}.1q, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d
|
| aarch64-neon-intrinsics.c | [all...] |
| /external/llvm/test/CodeGen/X86/ |
| mmx-arith.ll | 257 %tmp52 = tail call x86_mmx @llvm.x86.mmx.pmull.w( x86_mmx %tmp45, x86_mmx %tmp51 ) ; <x86_mmx> [#uses=2]
305 declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx)
|
| mmx-builtins.ll | 558 declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx) nounwind readnone
567 %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
581 %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vmul.ll | 112 ;CHECK: pmull.8h
115 %tmp3 = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
119 declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
[all...] |
| arm64-neon-3vdiff.ll | 3 declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>)
[all...] |
| /external/llvm/lib/Support/ |
| Host.cpp | 753 else if (CPUFeatures[I] == "pmull")
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| /external/valgrind/main/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/openssl/patches/ |
| 0014-arm_asm.patch | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | [all...] |
| /prebuilts/clang/linux-x86/host/3.5/bin/ |
| llvm-as | |
| llvm-dis | |
| llvm-link | |
| /prebuilts/sdk/tools/linux/ |
| libLLVM.so | |
| /frameworks/base/docs/html/tools/sdk/ndk/ |
| index.jd | 537 instruction sets: AES, CRC32, SHA2, SHA1, and 64-bit PMULL/PMULL2. (Issue
[all...] |
