| /external/clang/test/Sema/ |
| typecheck-binop.c | 21 int sub5(void *P, int *Q) { function
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| /external/llvm/test/CodeGen/Mips/ |
| stldst.ll | 28 %sub5 = add nsw i32 %6, -10
32 %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str, i32 0, i32 0), i32 %sub5, i32 %add6, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) nounwind
33 %call7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind
|
| /external/llvm/test/Transforms/LoopUnroll/ |
| 2011-08-08-PhiUpdate.ll | 9 ; CHECK: %sub5.lcssa = phi i32 [ %sub{{.*}}, %if.else{{.*}} ], [ %sub{{.*}}, %if.else{{.*}} ], [ %sub{{.*}}, %if.else{{.*}} ], [ %sub{{.*}}, %if.else{{.*}} ]
20 %sub = phi i32 [ %i, %if.else.lr.ph ], [ %sub5, %if.else ]
21 %sub5 = sub i32 %sub, %j
26 %i.tr = phi i32 [ %i, %entry ], [ %sub5, %if.else ]
|
| /external/llvm/lib/Target/R600/ |
| SIRegisterInfo.td | 67 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
78 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
120 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
131 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
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| AMDGPURegisterInfo.cpp | 52 AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
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| SIInstrInfo.cpp | 48 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
55 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
[all...] |
| /external/llvm/test/Transforms/InstCombine/ |
| div-shift-crash.ll | 69 %sub5.i.i.i.i = sub nsw i32 -701565022, %storemerge.i.i.i
70 %.sub5.i.i.i.i = select i1 %cmp.i.i.i.i, i32 -701565022, i32 %sub5.i.i.i.i
74 %div.i.i.i.i = udiv i32 %conv33.i.i.i, %.sub5.i.i.i.i
|
| /external/llvm/test/CodeGen/SystemZ/ |
| fp-sub-01.ll | 111 %sub5 = fsub float %sub4, %val5
112 %sub6 = fsub float %sub5, %val6
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| fp-sub-02.ll | 111 %sub5 = fsub double %sub4, %val5
112 %sub6 = fsub double %sub5, %val6
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| int-sub-04.ll | 133 %sub5 = sub i64 %sub4, %val5
134 %sub6 = sub i64 %sub5, %val6
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| int-sub-01.ll | 168 %sub5 = sub i32 %sub4, %val5
169 %sub6 = sub i32 %sub5, %val6
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| int-sub-02.ll | 173 %sub5 = sub i64 %sub4, %ext5
174 %sub6 = sub i64 %sub5, %ext6
|
| int-sub-03.ll | 173 %sub5 = sub i64 %sub4, %ext5
174 %sub6 = sub i64 %sub5, %ext6
|
| /external/llvm/test/CodeGen/X86/ |
| atomic_add.ll | 196 define void @sub5(i32* nocapture %p) nounwind ssp {
198 ; CHECK-LABEL: sub5:
|
| /external/llvm/test/CodeGen/PowerPC/ |
| 2011-12-05-NoSpillDupCR.ll | 46 %sub5.us = sub i64 31999, %indvars.iv20
47 %sext = shl i64 %sub5.us, 32
81 %sub5.us.1 = sub i64 31999, %indvars.iv20.1
82 %sext23 = shl i64 %sub5.us.1, 32
103 %sub5.us.2 = sub i64 31999, %indvars.iv20.2
104 %sext24 = shl i64 %sub5.us.2, 32
125 %sub5.us.3 = sub i64 31999, %indvars.iv20.3
126 %sext25 = shl i64 %sub5.us.3, 32
147 %sub5.us.4 = sub i64 31999, %indvars.iv20.4
148 %sext26 = shl i64 %sub5.us.4, 3
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 38 def sub5 : SubRegIndex;
59 let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
181 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 38 def sub5 : SubRegIndex;
59 let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
181 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
|
| /external/llvm/test/Analysis/DependenceAnalysis/ |
| Propagating.ll | 303 %sub5 = add nsw i64 %mul4, -18
304 %arrayidx7 = getelementptr inbounds [100 x [100 x i32]]* %A, i64 %sub5, i64 %sub, i64 %add
|
| SymbolicRDIV.ll | 243 %sub5 = sub i64 %j.03, %n1
244 %arrayidx6 = getelementptr inbounds i32* %A, i64 %sub5
|
| /external/llvm/test/Transforms/LoopVectorize/ |
| global_alias.ll | 645 %sub5 = sub nsw i32 %sub4, 1
648 %arrayidx7 = getelementptr inbounds [100 x i32]* %arrayidx6, i32 0, i32 %sub5
[all...] |
