Lines Matching refs:r_base
375 LIR* ArmMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) {
380 LIR* ArmMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
692 LIR* ArmMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,
694 bool all_low_regs = r_base.Low8() && r_index.Low8() && r_dest.Low8();
722 NewLIR4(kThumb2AddRRR, reg_ptr.GetReg(), r_base.GetReg(), r_index.GetReg(),
725 OpRegRegReg(kOpAdd, reg_ptr, r_base, r_index);
751 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg());
753 load = NewLIR4(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale);
758 LIR* ArmMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src,
760 bool all_low_regs = r_base.Low8() && r_index.Low8() && r_src.Low8();
789 NewLIR4(kThumb2AddRRR, reg_ptr.GetReg(), r_base.GetReg(), r_index.GetReg(),
792 OpRegRegReg(kOpAdd, reg_ptr, r_base, r_index);
816 store = NewLIR3(opcode, r_src.GetReg(), r_base.GetReg(), r_index.GetReg());
818 store = NewLIR4(opcode, r_src.GetReg(), r_base.GetReg(), r_index.GetReg(), scale);
824 LIR* ArmMir2Lir::LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base,
830 RegStorage r_ptr = r_base;
834 OpRegRegImm(kOpAdd, r_ptr, r_base, displacement & ~kOffsetMask);
854 LIR* ArmMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
860 bool all_low = r_dest.Is32Bit() && r_base.Low8() && r_dest.Low8();
869 load = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2Vldrd, r_base, displacement, r_dest);
873 load = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2LdrdI8, r_base, displacement, r_dest,
885 load = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2Vldrs, r_base, displacement, r_dest);
889 if (r_dest.Low8() && (r_base == rs_rARM_PC) && (displacement <= 1020) &&
894 } else if (r_dest.Low8() && (r_base == rs_rARM_SP) && (displacement <= 1020) &&
947 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), encoded_disp);
952 load = LoadBaseIndexed(r_base, reg_offset, r_dest, 0, size);
959 DCHECK(r_base == rs_rARM_SP);
965 LIR* ArmMir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
980 OpRegRegImm(kOpAdd, r_ptr, r_base, displacement);
984 load = LoadBaseDispBody(r_base, displacement, r_dest, size);
995 LIR* ArmMir2Lir::StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
1001 bool all_low = r_src.Is32Bit() && r_base.Low8() && r_src.Low8();
1010 store = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2Vstrd, r_base, displacement, r_src);
1013 store = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2StrdI8, r_base, displacement, r_src);
1024 store = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2Vstrs, r_base, displacement, r_src);
1028 if (r_src.Low8() && (r_base == rs_r13sp) && (displacement <= 1020) && (displacement >= 0)) {
1069 store = NewLIR3(opcode, r_src.GetReg(), r_base.GetReg(), encoded_disp);
1074 store = StoreBaseIndexed(r_base, r_scratch, r_src, 0, size);
1081 DCHECK(r_base == rs_rARM_SP);
1087 LIR* ArmMir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
1103 OpRegRegImm(kOpAdd, r_ptr, r_base, displacement);
1105 // We have only 5 temporary registers available and if r_base, r_src and r_ptr already
1107 // in LDREXD and recalculate it from r_base.
1118 OpRegRegImm(kOpAdd, r_ptr, r_base, displacement);
1129 null_ck_insn = StoreBaseDispBody(r_base, displacement, r_src, size);
1161 LIR* ArmMir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) {
