Cross Reference: /art/compiler/dex/quick/x86/target

Lines Matching refs:dalvikInsn
1686   switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {
1744   int num_vector_reg = mir->dalvikInsn.vA;
1787   int type_size = mir->dalvikInsn.vB;
1790   RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);
1791   uint32_t *args = mir->dalvikInsn.arg;
1830   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1831   RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);
1832   RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vB);
1838   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
1839   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
1879   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1880   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
1881   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
1882   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
1909   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1910   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
1911   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
1912   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
1940   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1941   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
1942   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
1943   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
1971   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
1975   int imm = mir->dalvikInsn.vB;
1977   switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {
2020   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2021   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2022   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2023   int imm = mir->dalvikInsn.vB;
2048   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2049   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2050   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2051   int imm = mir->dalvikInsn.vB;
2073   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2074   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2075   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2076   int imm = mir->dalvikInsn.vB;
2102   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2103   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2104   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
2110   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2111   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2112   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
2118   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2119   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2120   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
2132   const_mirp->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpConstVector);
2133   const_mirp->dalvikInsn.arg[0] = m0;
2134   const_mirp->dalvikInsn.arg[1] = m1;
2135   const_mirp->dalvikInsn.arg[2] = m2;
2136   const_mirp->dalvikInsn.arg[3] = m3;
2143   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2144   RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB);
2148   int vec_bytes = (mir->dalvikInsn.vC & 0xFFFF) / 8;
2236   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2238   RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB);
2239   int extract_index = mir->dalvikInsn.arg[0];
2276   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2277   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2278   RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);
2349   int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg);
2361   int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg);
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