Lines Matching refs:Address
47 void X86_64Assembler::call(const Address& address) {
49 EmitOptionalRex32(address);
51 EmitOperand(2, address);
69 void X86_64Assembler::pushq(const Address& address) {
71 EmitOptionalRex32(address);
73 EmitOperand(6, address);
97 void X86_64Assembler::popq(const Address& address) {
99 EmitOptionalRex32(address);
101 EmitOperand(0, address);
146 void X86_64Assembler::movq(CpuRegister dst, const Address& src) {
154 void X86_64Assembler::movl(CpuRegister dst, const Address& src) {
162 void X86_64Assembler::movq(const Address& dst, CpuRegister src) {
170 void X86_64Assembler::movl(const Address& dst, CpuRegister src) {
177 void X86_64Assembler::movl(const Address& dst, const Immediate& imm) {
194 void X86_64Assembler::movzxb(CpuRegister dst, const Address& src) {
212 void X86_64Assembler::movsxb(CpuRegister dst, const Address& src) {
221 void X86_64Assembler::movb(CpuRegister /*dst*/, const Address& /*src*/) {
226 void X86_64Assembler::movb(const Address& dst, CpuRegister src) {
234 void X86_64Assembler::movb(const Address& dst, const Immediate& imm) {
252 void X86_64Assembler::movzxw(CpuRegister dst, const Address& src) {
270 void X86_64Assembler::movsxw(CpuRegister dst, const Address& src) {
279 void X86_64Assembler::movw(CpuRegister /*dst*/, const Address& /*src*/) {
284 void X86_64Assembler::movw(const Address& dst, CpuRegister src) {
293 void X86_64Assembler::leaq(CpuRegister dst, const Address& src) {
301 void X86_64Assembler::movss(XmmRegister dst, const Address& src) {
311 void X86_64Assembler::movss(const Address& dst, XmmRegister src) {
361 void X86_64Assembler::addss(XmmRegister dst, const Address& src) {
381 void X86_64Assembler::subss(XmmRegister dst, const Address& src) {
401 void X86_64Assembler::mulss(XmmRegister dst, const Address& src) {
421 void X86_64Assembler::divss(XmmRegister dst, const Address& src) {
431 void X86_64Assembler::flds(const Address& src) {
438 void X86_64Assembler::fstps(const Address& dst) {
445 void X86_64Assembler::movsd(XmmRegister dst, const Address& src) {
455 void X86_64Assembler::movsd(const Address& dst, XmmRegister src) {
485 void X86_64Assembler::addsd(XmmRegister dst, const Address& src) {
505 void X86_64Assembler::subsd(XmmRegister dst, const Address& src) {
525 void X86_64Assembler::mulsd(XmmRegister dst, const Address& src) {
545 void X86_64Assembler::divsd(XmmRegister dst, const Address& src) {
684 void X86_64Assembler::xorpd(XmmRegister dst, const Address& src) {
704 void X86_64Assembler::xorps(XmmRegister dst, const Address& src) {
722 void X86_64Assembler::andpd(XmmRegister dst, const Address& src) {
732 void X86_64Assembler::fldl(const Address& src) {
739 void X86_64Assembler::fstpl(const Address& dst) {
746 void X86_64Assembler::fnstcw(const Address& dst) {
753 void X86_64Assembler::fldcw(const Address& src) {
760 void X86_64Assembler::fistpl(const Address& dst) {
767 void X86_64Assembler::fistps(const Address& dst) {
774 void X86_64Assembler::fildl(const Address& src) {
833 void X86_64Assembler::xchgl(CpuRegister reg, const Address& address) {
835 EmitOptionalRex32(reg, address);
837 EmitOperand(reg.LowBits(), address);
856 void X86_64Assembler::cmpl(CpuRegister reg, const Address& address) {
858 EmitOptionalRex32(reg, address);
860 EmitOperand(reg.LowBits(), address);
880 void X86_64Assembler::cmpq(CpuRegister reg, const Address& address) {
884 EmitOperand(reg.LowBits(), address);
896 void X86_64Assembler::addl(CpuRegister reg, const Address& address) {
898 EmitOptionalRex32(reg, address);
900 EmitOperand(reg.LowBits(), address);
904 void X86_64Assembler::cmpl(const Address& address, CpuRegister reg) {
906 EmitOptionalRex32(reg, address);
908 EmitOperand(reg.LowBits(), address);
912 void X86_64Assembler::cmpl(const Address& address, const Immediate& imm) {
914 EmitOptionalRex32(address);
915 EmitComplex(7, address, imm);
953 void X86_64Assembler::testq(CpuRegister reg, const Address& address) {
957 EmitOperand(reg.LowBits(), address);
1050 void X86_64Assembler::rex_reg_mem(bool force, bool w, Register* dst, const Address& mem) {
1072 void rex_mem_reg(bool force, bool w, Address* mem, Register* src);
1090 void X86_64Assembler::addq(CpuRegister dst, const Address& address) {
1094 EmitOperand(dst.LowBits(), address);
1107 void X86_64Assembler::addl(const Address& address, CpuRegister reg) {
1109 EmitOptionalRex32(reg, address);
1111 EmitOperand(reg.LowBits(), address);
1115 void X86_64Assembler::addl(const Address& address, const Immediate& imm) {
1117 EmitOptionalRex32(address);
1118 EmitComplex(0, address, imm);
1153 void X86_64Assembler::subq(CpuRegister reg, const Address& address) {
1157 EmitOperand(reg.LowBits() & 7, address);
1161 void X86_64Assembler::subl(CpuRegister reg, const Address& address) {
1163 EmitOptionalRex32(reg, address);
1165 EmitOperand(reg.LowBits(), address);
1201 void X86_64Assembler::imull(CpuRegister reg, const Address& address) {
1203 EmitOptionalRex32(reg, address);
1206 EmitOperand(reg.LowBits(), address);
1218 void X86_64Assembler::imull(const Address& address) {
1220 EmitOptionalRex32(address);
1222 EmitOperand(5, address);
1234 void X86_64Assembler::mull(const Address& address) {
1236 EmitOptionalRex32(address);
1238 EmitOperand(4, address);
1374 void X86_64Assembler::jmp(const Address& address) {
1376 EmitOptionalRex32(address);
1378 EmitOperand(4, address);
1409 void X86_64Assembler::cmpxchgl(const Address& address, CpuRegister reg) {
1413 EmitOperand(reg.LowBits(), address);
1461 movsd(dst, Address(CpuRegister(RSP), 0));
1474 xorps(f, Address::Absolute(reinterpret_cast<uword>(&float_negate_constant)));
1484 xorpd(d, Address::Absolute(reinterpret_cast<uword>(&double_negate_constant)));
1494 andpd(reg, Address::Absolute(reinterpret_cast<uword>(&double_abs_constant)));
1731 // return address then method on stack
1734 - kFramePointerSize /*return address*/;
1742 movsd(Address(CpuRegister(RSP), offset), spill.AsXmmRegister());
1748 movl(Address(CpuRegister(RSP), 0), method_reg.AsX86_64().AsCpuRegister());
1754 movq(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()),
1758 movl(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsCpuRegister());
1762 movsd(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
1765 movss(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
1781 movsd(spill.AsXmmRegister(), Address(CpuRegister(RSP), offset));
1813 movl(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
1816 movq(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
1820 movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow());
1821 movq(Address(CpuRegister(RSP), FrameOffset(offs.Int32Value()+4)),
1825 fstps(Address(CpuRegister(RSP), offs));
1827 fstpl(Address(CpuRegister(RSP), offs));
1832 movss(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
1834 movsd(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
1842 movl(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
1848 movq(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
1853 movl(Address(CpuRegister(RSP), dest), Immediate(imm)); // TODO(64) movq?
1858 gs()->movl(Address::Absolute(dest, true), Immediate(imm)); // TODO(64) movq?
1866 leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), fr_offs));
1867 gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister());
1871 gs()->movq(Address::Absolute(thr_offs, true), CpuRegister(RSP));
1886 movl(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1889 movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1893 movq(dest.AsRegisterPairLow(), Address(CpuRegister(RSP), src));
1894 movq(dest.AsRegisterPairHigh(), Address(CpuRegister(RSP), FrameOffset(src.Int32Value()+4)));
1897 flds(Address(CpuRegister(RSP), src));
1899 fldl(Address(CpuRegister(RSP), src));
1904 movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
1906 movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
1917 gs()->movl(dest.AsCpuRegister(), Address::Absolute(src, true));
1920 gs()->movq(dest.AsRegisterPairLow(), Address::Absolute(src, true));
1923 gs()->flds(Address::Absolute(src, true));
1925 gs()->fldl(Address::Absolute(src, true));
1930 gs()->movss(dest.AsXmmRegister(), Address::Absolute(src, true));
1932 gs()->movsd(dest.AsXmmRegister(), Address::Absolute(src, true));
1940 movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1947 movq(dest.AsCpuRegister(), Address(base.AsX86_64().AsCpuRegister(), offs));
1954 movq(dest.AsCpuRegister(), Address(base.AsX86_64().AsCpuRegister(), offs));
1960 gs()->movq(dest.AsCpuRegister(), Address::Absolute(offs, true));
1996 fstps(Address(CpuRegister(RSP), 0));
1997 movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
2000 fstpl(Address(CpuRegister(RSP), 0));
2001 movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
2015 movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), src));
2016 movl(Address(CpuRegister(RSP), dest), scratch.AsCpuRegister());
2024 gs()->movq(scratch.AsCpuRegister(), Address::Absolute(thr_offs, true));
2034 gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister());
2061 pushq(Address(CpuRegister(RSP), src));
2062 popq(Address(dest_base.AsX86_64().AsCpuRegister(), dest_offset));
2069 movq(scratch, Address(CpuRegister(RSP), src_base));
2070 movq(scratch, Address(scratch, src_offset));
2071 movq(Address(CpuRegister(RSP), dest), scratch);
2079 pushq(Address(src.AsX86_64().AsCpuRegister(), src_offset));
2080 popq(Address(dest.AsX86_64().AsCpuRegister(), dest_offset));
2088 movq(scratch, Address(CpuRegister(RSP), src));
2089 pushq(Address(scratch, src_offset));
2090 popq(Address(scratch, dest_offset));
2108 movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2120 leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2123 leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2135 movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2138 leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2141 leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2159 movq(out_reg.AsCpuRegister(), Address(in_reg.AsCpuRegister(), 0));
2174 call(Address(base.AsCpuRegister(), offset.Int32Value()));
2180 movl(scratch, Address(CpuRegister(RSP), base));
2181 call(Address(scratch, offset));
2185 gs()->call(Address::Absolute(offset, true));
2189 gs()->movq(tr.AsX86_64().AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true));
2194 gs()->movq(scratch.AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true));
2195 movq(Address(CpuRegister(RSP), offset), scratch.AsCpuRegister());
2210 gs()->cmpl(Address::Absolute(Thread::ExceptionOffset<8>(), true), Immediate(0));
2223 __ gs()->movq(CpuRegister(RDI), Address::Absolute(Thread::ExceptionOffset<8>(), true));
2224 __ gs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), true));
