Lines Matching refs:Address
216 // Patch the code at the current address with the supplied instructions.
229 // Patch the code at the current PC with a call to the target address.
231 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
232 // Patch the code at the current address with a call to the target.
978 uint32_t address) {
980 DCHECK(is_uint26(address));
981 Instr instr = opcode | address;
1806 // The Simulator will handle the stop instruction and get the message address.
2556 Address Assembler::target_address_at(Address pc) {
2562 return reinterpret_cast<Address>(
2566 // We should never get here, force a bad address if we do.
2568 return (Address)0x0;
2581 // On Mips, a target address is stored in a lui/ori instruction pair, each
2582 // of which load 16 bits of the 32-bit address to a register.
2583 // Patching the address must replace both instr, and flush the i-cache.
2585 // There is an optimization below, which emits a nop when the address
2588 void Assembler::set_target_address_at(Address pc,
2589 Address target,
2610 // li(t9, address); jalr(t9) (or jr(t9)).
2611 // If the destination address is in the same 256 MB page as the call, it
2613 // that lets the cpu pipeline prefetch the target address. However each
2614 // time the address above is patched, we have to patch the direct jal/j
2637 // the most simple one: if the address of the delay slot instruction is in
2667 uint32_t rd_field = ra.code() << kRdShift; // Return-address (ra) reg.
2694 void Assembler::JumpLabelToJumpRegister(Address pc) {
2695 // Address pc points to lui/ori instructions.
2710 uint32_t rd_field = ra.code() << kRdShift; // Return-address (ra) reg.
2727 CpuFeatures::FlushICache(pc + 2, sizeof(Address));
